Apparatus for performing analog multiplication and addition

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G06G 716

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056194447

ABSTRACT:
Apparatus for performing analog multiplication of a first value by a second value, including: 1) a variable capacitor whose capacitance represents the first value and 2) a second value voltage receiver, serially connected to the variable capacitor, wherein the second value voltage represents the second value, wherein a voltage level of the variable capacitor resulting from the provision of the second value voltage to the second value voltage receiver represents the multiplication of the first and second values.

REFERENCES:
patent: 4289035 (1981-09-01), Lee
patent: 4904964 (1990-02-01), Peng et al.
patent: 5008833 (1991-04-01), Agranat et al.
patent: 5089983 (1992-02-01), Chiang
M.A. Holler, "VLSI Implementations of Learning and Memory Systems: A Revi, Proceedings of Advances in Neural Information Processing Systems, V 3, Morgan Kaufman Pub., 1991.

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