Apparatus for patterning a semiconductor wafer

Details Apparatus for patterning a semiconductor wafer Apparatus for patterning a semiconductor wafer

2003-04-25

2004-10-26

Mathews, Alan (Department: 2851)

Photocopying

Projection printing and copying cameras

Focus or magnification control

C355S053000

Reexamination Certificate

active

06809800

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to a patterning apparatus and technique.
BACKGROUND OF THE INVENTION
Semiconductors are widely used for integrated circuits for electronic applications, including radios, televisions, and personal computing devices, as examples. Such integrated circuits typically include multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. Many integrated circuits now include multiple levels of metallization for interconnections.
The fabrication of semiconductor devices involves depositing or forming metallization and dielectric layers, as well as active component layers. Each layer must be patterned with a desired pattern in order for the semiconductor devices to function properly. A patterning process typically involves depositing a photoresist that may comprise an organic polymer, for example, over a semiconductor wafer layer. The photoresist is exposed through a mask to transfer the pattern of the mask to the photoresist. Either exposed or unexposed portions of the photoresist are removed during subsequent development, depending on whether a positive or negative lithographic resist process is used. The photoresist portions remaining on the semiconductor wafer surface shield the top wafer surface during an etch process to leave the top semiconductor wafer layer residing in regions where photoresist remain.
A prior art apparatus
10
for patterning the surface of a semiconductor wafer
30
is shown in
FIG. 1. A
stage
12
is adapted to support a semiconductor wafer
30
. The stage
12
is adapted to move the entire wafer
30
from position to position in order to expose portions of the wafer
30
surface during the patterning process. The stage
12
may be mounted on a base, not shown. The stage
12
is adapted to securely hold the wafer
30
in place. A lens
20
is disposed above the wafer
30
. Lens
20
typically comprises a demagnification lens that reduces the image transferred to the wafer
30
by 4-5×, for example. Alternatively, no lens
20
may be required if a 1:1 ratio magnification scheme is used for transferring the pattern from the mask
18
to the wafer
30
. A mask
18
having the desired pattern to be transferred to the wafer
30
is disposed above lens
20
. A light source
16
is disposed above mask
18
, as shown.
To pattern the wafer
30
, the light source
16
which may comprise a laser, for example, is illuminated. The light passes through the mask
18
, through demagnification lens
20
, and exposes the top surface of the semiconductor wafer
30
.
There are various types of exposure tools that function similar to the apparatus
10
described and illustrated in FIG.
1
. In a step and repeat apparatus, the mask
18
pattern is transferred onto a section of the wafer
30
at a time, and a stage
12
moves the wafer
30
from point to point, exposing the wafer
30
surface in a plurality of steps.
An alternative apparatus used to pattern and expose a wafer
30
surface is known as a step and scan apparatus. Because the demagnification lens
20
is typically non-planar, the pattern of an image passed through the lens
20
may be distorted at the edges of the lens
20
. A step and scan apparatus exposes the wafer
30
surface to a pattern through a fixed slit in a plate disposed between the light source and the lens
20
. The mask
18
is moved at the same speed as the wafer
30
to expose and pattern the wafer
30
surface for 1:1 exposure, for example. Alternatively, the mask
18
may be moved at a different speed as the wafer
30
, to correlate with the demagnification or magnification of the lens
20
. For example, in the prior art, if a 4:1 demagnification lens is used, the mask
18
is moved at a speed 4 times faster than the wafer
30
is moved during the exposure process. Prior art step and scanners synchronize the scan speed of the mask
18
with the speed of the wafer
30
in accordance with the magnification of the lens.
FIG. 2
illustrates a top view of a mask
18
having transparent regions or holes
22
therein. A portion of a wafer
30
top surface is also shown, having much smaller dimensions than the mask
18
due to demagnification. Wafer regions
26
represent exposed portions of the semiconductor wafer
30
surface after patterning the wafer
30
using mask
18
.
A problem with prior art patterning methods and apparatuses is that the islands
24
between the holes
22
in mask
18
are becoming smaller and smaller to meet the increased demands for miniaturization in semiconductor devices. As semiconductor devices are made smaller, it becomes more and more difficult to properly manufacture the devices. For example, holes
22
in mask
18
may represent an array of storage nodes of dynamic random access memory (DRAM) cells.
A mask
18
must be inspected for defects to insure that the proper pattern will be transferred to the wafer
30
. The inspection dimensions have a lower limit, for example, on the order of 400 nanometers at the time of the filing of this patent. Typically, an optical microscope is used to inspect the mask in a die-to-die inspection or a die-to-database inspection, as examples. Therefore, the miniaturization of semiconductor devices is limited by the ability to inspect the patterning mask
18
. Another problem is that different wavelengths of light are used to inspect the mask
18
than are used to expose a wafer
30
, so not all mask
18
problems are detected, or are not accurately detected.
Furthermore, a transfer problem called line shortening may occur when the mask
18
pattern is transferred to the semiconductor wafer
30
surface.
FIG. 2
shows shortened dimensions
32
alongside holes
26
. Shortened dimensions
32
may actually be transferred to the wafer
30
surface rather than pattern size
26
due to the optics involved in transferring the exposure light through the mask
18
and lens
20
. Essentially, the desired pattern
26
shrinks to an undesired smaller size represented by rectangle
32
. This results in an increased size island
34
between rectangular patterns
32
.
Another prior art solution to address line shortening is double exposure or micro-stepping, which decreases the throughput, e.g. increases the time required to process a wafer. A single exposure step process is preferred because alignment problems and overlay problems can be introduced with double exposure. However, certain semiconductor lithography patterns, such as DRAM deep trench cells, are not printable on size in a single exposure step with state of the art exposure and mask-making capabilities, because extreme biases are required in the long axis of the features. The extreme biases are needed to compensate for line shortening at the exposure step. The extreme biases result in islands on the mask
30
that are too small to be inspected.
What is needed in the art is a patterning method and apparatus that alleviates the mask inspection limitations and alignment problems, and compensates for line shortening, problematic in the prior art.
SUMMARY OF THE INVENTION
These problems are generally solved or circumvented by the present invention that achieves technical advantages as a method and apparatus for patterning the surface of a semiconductor wafer. A mask is moved at a different speed than the wafer in a ratio different than the magnification factor during the scanning process to achieve more accurate, smaller dimensions on a wafer surface.
Disclosed is a process for patterning a semiconductor wafer, comprising covering the surface of the wafer with a patterned mask, and transferring the mask pattern to the wafer surface at a particular magnification factor, wherein transferring the mask pattern comprises exposing portions of the wafer surface while moving the wafer horizontally at a first speed and simultaneously moving the mask horizontally at a second speed, the first and second speeds being different from one a

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