Patent
1998-06-04
1999-11-09
Harrell, Robert B.
G06F 942
Patent
active
059830000
ABSTRACT:
Apparatus for patching a control program in a processor which executes a control program stored in non-volatile memory, and which has access to a plurality of patch routines. The apparatus comprises storage for storing trap addresses each of which is associated with the address of a patch routine; a comparator for comparing the address of the program counter with the patch addresses; and a diverter for responding to a positive comparison by diverting the control program to the patch routine whose address is associated with the trap address that gave rise to the positive comparison. Each trap address is associated with one of the possible operating states of the processor. The apparatus includes a selector for selecting a predetermined number of trap addresses from the trap addresses stored in the storage so as to select trap addresses that are associated with the current operating state of the processor. The comparator compares the address in the program counter with the selected addresses only.
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patent: 5404527 (1995-04-01), Irwin et al.
patent: 5796974 (1998-08-01), Goddard et al.
Alcatel
Harrell Robert B.
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