Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-06-03
2001-10-23
Ngo, Chuong Dinh (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06308189
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processors, and in particular, to logical shift operations in data processors.
BACKGROUND INFORMATION
Vector processing extensions to scalar microprocessor architectures are being implemented to enhance microprocessor performance, particularly with respect to multimedia applications. One such vector processing extension is the Vector Multimedia Extension (VMX) to the POWERPC microprocessor architecture. (“PowerPC” is a trademark of IBM Corporation.) VMX is a single instruction multiple data (SIMD) architecture. In a SIMD architecture, a single instruction operates on multiple sets of operands. For example, in a 128-bit SIMD architecture, an instruction may operate on sixteen 8-bit operands, eight 16-bit operands, four 32-bit operands, or one 128-bit operand.
Logical shift operations within the VMX instruction set require the implementation of a shifter in the microprocessor hardware incorporating the VMX extension. In general, a 128-bit barrel shifter is expensive to implement. Furthermore, in a VMX implementation in which logical shifts do not require a full 128-bit shift, realizing a full 128-bit barrel shifter wastes resources.
Thus, there is a need in the art for a mechanism to implement partial logical shifts in vector processing hardware which obviates the need for a 128-bit barrel shifter.
SUMMARY OF THE INVENTION
The previously mentioned needs are addressed with the present invention. Accordingly, there is provided, in a first form, an apparatus for generating partial logical shifts of a logical signal. The apparatus includes a plurality of barrel shifters, each barrel shifter having an input adapted for receiving a portion of the logic signal, and a plurality of logic circuits, each logic circuit having a first input coupled to an output of a corresponding barrel shifter. A first subset of the plurality of logic circuits has a second input coupled to an output of a succeeding barrel shifter, and a second subset of the plurality of logic circuits has a third input coupled to an output of a preceding barrel shifter. An output of each logic circuit outputs a portion of a partially shifted logic signal, the output of each logic circuit being a logical combination formed in response to the output of the corresponding barrel shifter and the second and third input signals.
There is also provided, in a second form, a method of generating m-bit partial logical shifts of a logical signal. The method includes rotating each portion of a plurality of portions of the logical signal by m-bits, thereby forming a plurality of corresponding rotated portions. Each of the rotated portions is masked with a preselected mask signal, and with a complementary mask formed by complementing the preselected mask signal. Each logical output from the step of masking with a preselected mask is logically combining with a preselected one of each logical output from the step of masking with the complementary mask to form a portion of an m-bit shifted output logical signal.
Additionally, there is provided, in a third form, a data processing system. The data processing system includes an instruction dispatch device adapted for retrieving instructions from an instruction storage device, a partial logical shift device coupled to the instruction dispatch device and generating a partially shifted output signal from a logic signal received from the dispatch device in response to instructions therefrom. The shift device comprises a plurality of barrel shifters, each barrel shifter having an input adapted for receiving a portion of the logic signal, a plurality of logic circuits, each logic circuit having a first input coupled to an output of a first predetermined barrel shifter, and a second input coupled to an output of a second predetermined barrel shifter, wherein each of the logic circuits outputs a portion of the shifted output signal, the output of each logic circuit being a logical combination formed in response to the first and second inputs.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
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patent: 5729482 (1998-03-01), Worrell
Carwell Robert M.
International Business Machines - Corporation
Newberger Barry S.
Ngo Chuong Dinh
Winstead Sechrest & Minick P.C.
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