Apparatus for parallel decoding of variable length encoded image

Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes

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H03M 740

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active

055681395

ABSTRACT:
In an apparatus for the parallel decoding of encoded image signals separated into variable length encoded blocks, wherein the encoded blocks are distributed over N buffer memories included in N parallel decoding paths at a demultiplexor, a provisional buffer memory circuit is provided between the demultiplexor and the N buffer memories. The circuit serves to, upon receiving an encoded block destined to one of the N buffer memories, temporarily hold the received block therein until the designated buffer memory becomes available for the received block. However, when the designated buffer memory is immediately available for the received block, the circuit dispatches it to the buffer memory without such temporary holding.

REFERENCES:
patent: 5138315 (1992-08-01), LeQueau et al.
patent: 5216503 (1993-01-01), Paik et al.
patent: 5239308 (1993-08-01), Keesen
patent: 5386212 (1995-01-01), Shen
patent: 5386213 (1995-01-01), Haupt
Hidenori Okuda et al., "A Concurrent Decoding Scheme for Multiple Motion Videos" Jun. 1991, ICC. 91, International Conference on Communication pp. 501-505 Jun. 1991.
Note "AL" Above Not Seen or Considered by Examiner TLG.

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