Apparatus for parallel calculation of prediction bits in a...

Details Apparatus for parallel calculation of prediction bits in a... Apparatus for parallel calculation of prediction bits in a...

2007-09-11

2007-09-11

Hung, Yubin (Department: 2624)

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C382S234000, C348S394100, C375S240240

Reexamination Certificate

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10604567

ABSTRACT:
A storage device stores rows of bits including a D0bit, an X0bit, an X1bit, a Y0bit, a Y1bit and a spatially predicted coded block pattern having an A0bit, an A1bit, an A2bit, and an A3bit. A first circuit is connected to the storage device for setting the A0bit. A second circuit is connected to the storage device for setting the A2bit and operates in parallel to the first circuit. In a second clock cycle, the bits in the storage device are shifted and the first circuit and the second circuit are reused to calculate the A1bit and the A2bit in parallel. Alternatively, a third circuit and a fourth circuit can be connected to the storage device to calculate the A1 bit and the A2bit in parallel during the first clock cycle.

REFERENCES:
patent: 4469916 (1984-09-01), de Bergh et al.
patent: 5001560 (1991-03-01), Ericsson
patent: 5717462 (1998-02-01), Hayashi
patent: 6012156 (2000-01-01), Zydek et al.
patent: 6563953 (2003-05-01), Lin et al.
patent: 2005/0254605 (2005-11-01), Holmes et al.

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