Apparatus for page mode programming of an EEPROM cell array with

Details Apparatus for page mode programming of an EEPROM cell array with Apparatus for page mode programming of an EEPROM cell array with

1990-07-10

1992-03-31

Gossage, Glenn

Static information storage and retrieval

Floating gate

Particular biasing

3652385, 365195, G11C 1606

Patent

active

051013797

ABSTRACT:
An apparatus for page mode programming of an EEPROM cell array with false loading protection is disclosed. The system includes a flip-flop operatively connected to a bit line for storing information to be loaded into an EEPROM memory cell, and false loading protection circuitry operatively connected to the bit line for preventing the false loading of an erroneous signal into the flip-flop and/or an EEPROM cell.

REFERENCES:
patent: 4460982 (1984-07-01), Gee et al.
patent: 4599707 (1986-07-01), Fang
patent: 4694427 (1987-09-01), Miyamoto et al.
patent: 4725984 (1988-02-01), Ip et al.
patent: 4730274 (1988-03-01), Edwards
patent: 4785424 (1988-11-01), Lin et al.
Mehrotra, "A 64Kb CMOS EEPROM with On-Chip ECC", IEEE ISSCC, Feb. 23, 1984, pp. 142-143, 328.

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