Apparatus for page mode programming of an EEPROM cell array with

Details Apparatus for page mode programming of an EEPROM cell array with Apparatus for page mode programming of an EEPROM cell array with

1986-05-27

1988-11-15

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365204, 365230, G11C 700, G11C 1140

Patent

active

047854243

ABSTRACT:
An apparatus for page mode programming of a memory cell with false loading protection is disclosed. The apparatus discharges any residual voltage left on the bit line after a read operation to prevent this voltage from being erroneously loaded into temporary storage apparatus associated with the bit line. In a preferred embodiment, two transistors are placed in series between the bit line and the array V.sub.ss line. A first transistor is controlled by a signal indicating that information is to be loaded into the temporary storage apparatus. The second transistor is controlled by a signal indicating that no memory cell associated with the bit line has been selected for programming.

REFERENCES:
patent: 4110842 (1978-08-01), Sarkissian et al.
patent: 4130900 (1978-12-01), Watanabe
Mehrotra, "A 64Kb CMOS EEROM with On-Chip ECC", IEEE ISSCC Digest of Technical Papers, Feb. 23, 1984, pp. 142-143, 328.

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