Apparatus for operand data bypassing having previous operand sto

Details Apparatus for operand data bypassing having previous operand sto Apparatus for operand data bypassing having previous operand sto

1994-12-27

1997-06-10

Ellis, Richard L.

G06F 934

Patent

active

056385269

ABSTRACT:
A register read control method for use with an information processing apparatus for executing a plurality of instructions in parallel during pipeline processing. The apparatus includes a register file, a register designation selector, a cache register, a selector, an arithmetic circuit, a register cache pass and a comparator. When the comparator detects a coincidence between the data in the cache register for the current instruction and the operand in the next instruction, the comparator causes the selector to select the register cache pass as input thereto and to move the contents of the cache register back directly to the cache register via the register cache pass.

REFERENCES:
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patent: 5043868 (1991-08-01), Kitamura et al.
patent: 5123108 (1992-06-01), Olson et al.
patent: 5148529 (1992-09-01), Ueda et al.
patent: 5222240 (1993-06-01), Patel
patent: 5404552 (1995-04-01), Ikenaga
IBM Technical Disclosure Bulletin, vol. 27, No. 8, Jan. 1985, New York, US, p. 4646, Olnowich and Vanding "Means for Executing Register to Register Instructions in a Computer with a Single Port Local Store".

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