Apparatus for obtaining reduced pin count packaging and methods

Details Apparatus for obtaining reduced pin count packaging and methods Apparatus for obtaining reduced pin count packaging and methods

1984-09-19

1987-04-07

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 68, 370 63, H04Q 1104

Patent

active

046566201

ABSTRACT:
In order to reduce hardware cost, apparatus is disclosed for reducing the pin count or terminal count of circuit modules in a large digital system, resulting in condensed packaging and the elimination of huge connecting structures and backplane orientations in such systems. The apparatus depicted employs a time division bus to serially carry data from a plurality of terminal locations and to demultiplex the serial data by means of a demultiplexer to provide a plurality of output logic states on a plurality of parallel data lines. These data lines are directed to a logic array circuit which can perform predetermined logic operations on the data prior to transmission of the same to associated backplanes in the system. The outputs from the logic array circuit are multiplexed to provide a time division serial output bus for transmission to the back planes or shelves of other modules in the system. The entire apparatus as the demultiplexer, the logic array and the multiplexer are preferably contained on the same VLSI chip card or board resulting in a substantial reduction in terminals or pins required for transmission to other system modules.

REFERENCES:
patent: 4179587 (1979-12-01), Herchtal
patent: 4292623 (1981-09-01), Eswaran et al.
patent: 4335456 (1982-06-01), Gaiser et al.
patent: 4412322 (1983-10-01), Briley et al.

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