Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-06-19
2004-02-03
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06687726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention lies in the electronics field. More specifically, the invention relates to an apparatus for multiplication by a constant coefficient, in which, for example, the multiplier is processed in the form of a shift number and further information.
Such an apparatus is known from the Proceedings of the IEEE Conference ISCAS 85, p. 1389-90. The document explains that, for multiplication by constant coefficients, it is advantageous to store the multiplier in CSD code in such a way that the control unit reads the shift number and the sign directly from a coefficient memory without recoding.
2. Summary of the Invention
It is accordingly an object of the invention to provide an apparatus for multiplying with constant factors and a video compression method (MPEG), which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which the required circuit area is as small as possible, and the processing speed is as high as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, an apparatus for multiplication by constant factors, comprising:
a table outputting, in dependence on a code, a factor element and a shift element of a multiplier;
a bit-reduced multiplication device having an input receiving the factor element and an output;
a shift device having an input connected to the output of the bit-reduced multiplication device and having a control signal input;
the shift device receiving the shift element as a control signal with the number of shift steps; and
the shift device outputting a final result of a multiplication with a respective constant factor.
In accordance with an added feature of the invention, the table is configured such that the shift device is designed for a single shift direction.
In accordance with an additional feature of the invention, the table is configured such that the shift element is constant and/or the factor element corresponds substantially to the code for the multiplier.
In accordance with another feature of the invention, the table is configured such that as many factor elements as possible are of equal magnitude.
With the above and other objects in view there is also provided, in accordance with the invention, a video compression method performed with the above-outlined apparatus, which comprises:
inputting a code of an input variable quantization scale, wherein the multiplier corresponds to a scaling factor defined by the quantization scale;
forming the bit-reduced multiplication device as a series circuit formed of a first multiplier, a cache member, and a second multiplier, and supplying a first input of the first multiplier with a factor element of the scaling factor, supplying a second input of the first multiplier with values from a quantization matrix, and further supplying the second multiplier with input data; and
carrying out division by a power of the number 2 with the shift device in dependence on the shift element of the scaling factor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an apparatus for multiplying with constant factors and a video compression method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
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Japanese Patent Abstract No. 57041738 (Shigenori), dated Mar. 9, 1982.
“Multiplication by Integer Constants” (Wiley & Sons), dated Jul. 1986, Software Practice & Experience, vol. 16, No. 7, pp. 641-652.
“Parallel-Serial Multiplication Using Booth's Algorithm And Horner's Scheme” (Stölzle et al.), dated 1985, Siemens, AG, Central Reserch Development, pp. 1389-1390, as mentioned on p. 1 of the specification.
Greenberg Laurence A.
Infineon - Technologies AG
Malzahn David H.
Mayback Gregory L.
Stemer Werner H.
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