Electricity: conductors and insulators – Anti-inductive structures – Conductor transposition
Reexamination Certificate
2000-03-16
2001-09-25
Reichard, Dean A. (Department: 2831)
Electricity: conductors and insulators
Anti-inductive structures
Conductor transposition
C174S050510, C174S050510, C439S066000, C439S607070, C361S816000, C361S717000, C361S718000, C257S712000, C257S713000, C257S660000
Reexamination Certificate
active
06294731
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor packaging, particularly to multi-chip semiconductor packaging.
BACKGROUND OF THE INVENTION
Throughout the 1970s and 1980s semiconductor packaging was relatively stable, with changes occurring gradually over periods of five to ten years. The U.S. military was the major technology driver—controlling standards, testing and managing change. During the 1970s, one major focus in packaging was in cost reduction—producing a semiconductor package at lower cost. From 1984 to through 1994, change was gradual, the largest change being a gradual transition to surface mount technology (SMT). Over that ten year period, approximately 50% of the industry converted to SMT, which illustrated how slowly new technologies may be introduced into electronics packaging.
However, with the growth of the consumer and industrial electronics industry and the simultaneous decline of the military market, rapid changes have occurred in the electronics industry. As a result, the U.S. electronics market may be starting to operate much like the Japanese consumer electronics market—with higher pressures to reduce costs and shrink packaging size.
To meet such demands, integrated circuit (IC) manufacturers have begun integrating more circuit functions, shrinking device features, and increasing speeds. From a packaging perspective, smaller form factors, requirements for more input/output signals and power management all became major technology drivers. System level needs included the transition to SMT and use of finer featured packages. Sophisticated new products of all types began developing, and soon barriers were reached with conventional packages and processes.
Conventional package leads may be deemed too fine and fragile, and surface mounting processes have not proved to be robust enough to provide acceptable yields. The 208-lead Plastic Quad Flat Package (QFP), illustrated in
FIG. 8
, became the appropriate practical limit for peripheral leaded packages—and the transition to grid array packages began.
To further enable compatibility with surface mount technology (SMT) process, solder balls were attached at the bottom of land grid array packages, forming the Ball Grid Array (BGA), illustrated in FIG.
9
. The BGA package allows for much greater I/O counts while eliminating the fragile and difficult aspects of the conventional QFP.
A number of derivatives of the BGA (e.g., FPGA, &mgr;BGA, or he like) are in existence today. The BGA package comprises a ceramic substrate with a multi-layer interconnect. On the top of the package, a single die or multiple dice may be attached by wire bond or flip-chip to the substrate. The bottom of the package comprises of an array of solder balls with diameters ranging from 0.4 mm and higher.
For improved reliability, an under-fill maybe used to fill the space between the solder balls following solder attach of the BGA package. A number of variants of the BGA structure may be based on the use of different substrate material including ceramic in CBGA, plastic encapsulated FR-4 in PBGA and flexible circuits in FBGA.
BGA packages were first designed by Motorola to solve space constraint problems in portable communications products. Motorola initially used a 2 layer PCB as a package substrate and in manufacturing, used conventional die attach, bonding, molding and solderball attach. Such a design provided a robust yet small footprint package, used to package lower I/O communications chips.
Soon others manufacturers tested packages in higher pin count applications. It quickly became apparent that BGAs could enable cost effective high I/O packages without causing major manufacturing changes for users. In fact, the BGAs were so robust most users report a 10× or greater reduction in solder defects. BGAs enabled great improvements in users manufacturing efficiencies and corresponding cost reductions. BGAs also provided superior electrical performance, as electrical paths were shorter and power/ground planes could be added to the package.
Although BGA structures have inherent high yield assembly, the long term reliability of the interconnect may be compromised without the use of under-fill. Also, these packages are associated with perimeter array contacts which have potentially greater parasitics which may degrade the electrical performance of high clock rate applications.
For package de-mountability, a number of area array interposers/electronic connectors have been developed, and are described below. Each of the approaches uses an area array configuration to form an electrical connection between two parallel substrates which may be clamped or secured together. This connector type can be traced back to July of 1970, with U.S. Pat. No. 3,638,163. Subsequent developments used metallized and metal filled elastomeric cylinders within an array as described in U.S. Pat. No. 3,985,413.
AMP has developed the Micro Interposer™ that is based upon an area array separable socket-connector constructed with the aid of a miniature structure which resembles the shape of an omega. The Micro Interposer™ uses a retaining housing and when compressed into its contacting position, provides low resistance contacts. The Micro Interposer™ is formed by inserting the contacts into cavities formed in photo-defined laminates. Further details of the Micro Interposer™ are disclosed in
AMP Journal of Technology
, Vol. November 1, 1991 (D. G. Grabbe and H. Merkelo), incorporated herein by references.
Another concept developed by AMP uses canted coiled spring contacts positioned in openings within the connector to provide electrical contact between the two intended substrates. In U.S. Pat. Nos. 5,007,842 and 5,030,109 both of which are incorporated herein by reference, the above approach describes the coiled spring contact. This coiled spring contact approach is also disclosed in an earlier U.S. Pat. No. 4,655,462, incorporated herein by reference, which also used canted springs between parallel substrates.
Another concept developed by AMP uses a conductive gel inserted into cavities within an elastomeric body again to form interconnections between two parallel substrates. The structure, described in U.S. Pat. No. 5,123,849 incorporated herein by reference, illustrates how this area array connector could be used to interface an active component to an interconnect substrate.
Through use of miniature springs, E-tec Interconnect has developed an interposer/socket technology for area array devices. The springs may be compressed between two mating members within a fiberglass laminate structure with drilled holes for the vertical interconnect assembly. The solder-less version of their product line has many characteristics of an interposer.
The minimum possible pitch on the E-tec interconnect devices approaches 1 mm with an insertion force of approximately 35 grams per contact. This technology has been used as an area array socket due to its overall size and thickness. In addition, the high cost and no viable path to high volume manufacturing has limited to impact of the technology.
The semiconductor industry, in conjunction with several technical committees and associations have developed road maps for development of next generation products and associated technologies. Industries such as computing, communications and portable electronics have been driving these requirements and the associated road maps.
As an extension of the semiconductor industry, the electronics packaging industry has also witnessed similar technological and market dynamics. Packaging and materials engineering and development are at the very core of these next generation electronics insertion strategies outlined in these road maps. Future electronic systems may be more intelligent, have higher density, use less power, operate at higher speed, and may include mixed technology devices and assembly structures at lower cost than today.
The rapidly growing portable electronics market, e.g. cellular phones, laptop computers, and PDAs, are an integral facet of modern life.
Keating John T.
Lu Dau-Tsuong
Ngo Hung V
Performance Interconnect, Inc.
Reichard Dean A.
Salzman & Levy
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