Apparatus for minimizing a clock skew occurring in a semiconduct

Details Apparatus for minimizing a clock skew occurring in a semiconduct Apparatus for minimizing a clock skew occurring in a semiconduct

1998-06-26

2000-06-27

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327293, 327295, H03K 514

Patent

active

06081148&

ABSTRACT:
A clock circuit is used in a semiconductor device having a control block and a macroblock in order to provide synchronous clocks. The clock circuit contains a clock source for generating the clocks; a clock tree, coupled between the clock source and the control block and the macroblock, for relaying the clocks to the control block and the macrobock; and programmable delays coupled between the clock source and the clock tree and between the clock tree and the control block and the macroblock in order to reduce overall clock skew.

REFERENCES:
patent: 5369640 (1994-11-01), Watson et al.
patent: 5686845 (1997-11-01), Erdal et al.
patent: 5784600 (1998-07-01), Doreswamy et al.

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