Apparatus for microprocessor address bus testing

Details Apparatus for microprocessor address bus testing Apparatus for microprocessor address bus testing

1982-04-01

1984-10-02

Smith, Jerry

Excavating

371 20, G06F 1100

Patent

active

044751958

ABSTRACT:
An address bus of a central processor unit (CPU) is tested by generating repetitive "no operation" (NO OP) instructions. A microprocessor in the CPU receives the NO OP instruction code set manually into switches and generates sequential addresses on successive CPU cycles on the address bus. The microprocessor generates a read signal during each CPU cycle which is jumpered to portions of the logic to allow continuity of operation during test.

REFERENCES:
patent: 3988603 (1976-10-01), Griffin
patent: 4308615 (1981-12-01), Koegel et al.
Farly, When Logic Analyzers Meet Development Systems, 9-13-1979, Electronics, p. 141.
Lowry, Skillfully Used Logic Analyzers Solve Problems Large and Small, EDN, Apr.20, 1977, p. 86.

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