Apparatus for measuring a memory device

Coded data generation or conversion – Sample and hold – Having variable sampling rate

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348537, H03M 100

Patent

active

058050922

ABSTRACT:
In apparatus that measures the characteristics of the read-out signals from memory media, in the prior art, phase control of the clock signals for synchronized sampling of the measurement apparatus was performed by using the read-out signals. Synchronization discrepancies and inability to perform synchronization were produced due to the quality of the read-out signals. In the invention, a Logical processing part generates selection signals that control the selection of samples with phase information, for performing synchronization, from test signals of a recording part, which records the same signal train as the test signal train written onto the memory medium. By the control of these selection signals, samples with phase information for performing synchronization are selected from the sample train output from an A/D converter through an equalizer; these samples pass through a selection part and a control clock generating part by means of the processing of a feed-back processing part. The samples with phase information are fed back, and correct phase control is performed.

REFERENCES:
patent: 4905085 (1990-02-01), Faulhaber
patent: 5572556 (1996-11-01), Satoh
Timing Recovery in Digital Synchronous Data Receivers -IEEE Trans. Comm. May 1976, No. 5, pp. 516-530.
Timing Recovery in Synchronous Equalized Data Communications -IEEE Trans. Comm. Feb. 1975, No. 2, pp. 269-274.
Timing Recovery for Equalized Partial Response Systems -IEEE Trans. Comm. Dec. 1976, No. 12, pp. 1326-1331.

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