Apparatus for masking data bits

Details Apparatus for masking data bits Apparatus for masking data bits

1991-08-19

1992-06-23

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular input circuit

377 54, 377111, H03K 2140

Patent

active

051250110

ABSTRACT:
A system for masking bits in a configuration. The system has a bus with first and second sets of bit lines. A line from the first set is paired with aline from the second set; the paried lines are coupled to each cell in the configuration register. A logic circuit is connected to each register cell and the corresponding paired lines. Depending upon the state of the bit signal of the second set bit line, the logic circuit passes the bit signal on the first set bit line for loading into the register cell or reloads the bit line signal already in the register cell. In this manner, masking operations in the configuration register can be performed very quickly.

REFERENCES:
patent: 4034301 (1977-07-01), Kashio
patent: 4396829 (1983-08-01), Sugihara et al.
patent: 4866742 (1989-09-01), Fujiyama et al.
patent: 4893028 (1990-01-01), Beltramini

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