Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Patent
1997-06-25
2000-05-02
Vu, Viet D.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
712214, 712216, G06F 938
Patent
active
060584726
ABSTRACT:
A system, apparatus and method for ensuring program correctness in an out-of-order processor spite of younger load instructions being boosted past an older store utilizing a memory disambiguation buffer ("MDB"). The memory disambiguation buffer stores all memory operations that have not yet been retired. Each entry has several fields amongst which are the data and the addresses of the memory operations. An incoming load checks its address against the addresses of all the stores. If there is a match against an older store, then the load must have received old data from the data cache and the load operation is replayed to seek data from the memory disambiguation buffer on the replay. If on the other hand, there were no matches on any older store, the load is assumed to have received the right data from the data cache (assuming a data cache hit). An incoming store checks its address against the addresses of all younger loads. If there is a match against any younger load, then the younger load is replayed along with all of its dependents.
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Chidambaran P.K.
Hetherington Ricky C.
Panwar Ramesh
Barton Steven K.
Kubida William J.
Sun Microsystems Inc.
Vu Viet D.
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