Patent
1993-03-09
1994-11-01
Dixon, Joseph L.
395425, G06F 1300, G06F 1208
Patent
active
053613406
ABSTRACT:
A computer system includes first and second processors each having a virtual cache memory, a main memory, a bus coupled to the main memory and the processors, and apparatus for addressing the cache associated with each processor for providing that the data in each virtual cache stores data from the same physical location in main memory at a same index position in each virtual cache, a memory management unit (MMU) coupled to each processor such that addressing information is transferred to each memory management unit to indicate the virtual address of data to be written to the virtual cache, the memory management unit generating from the virtual address a physical address, and determining whether any other virtual cache includes data from the same physical memory positions.
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Cekleov Michel
Dubois Michel
Kelly Edmund
Dixon Joseph L.
Lane Jack A.
Sun Microsystems Inc.
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