Patent
1994-10-14
1997-04-22
Treat, William M.
395473, G06F 1200
Patent
active
056236298
ABSTRACT:
A data processor for maintaining coherency of data in a cache memory. The processor includes two memory-data-coherency maintaining devices and an operation mode changing device for changing a combination of operation modes of the maintaining devices, thereby enabling one kind of data processor to be adaptable to a plurality of different system structures and optimum memory-data-coherency to be maintained.
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Mitsubishi Denki & Kabushiki Kaisha
Treat William M.
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