Apparatus for low skew system clock distribution and generation

Details Apparatus for low skew system clock distribution and generation Apparatus for low skew system clock distribution and generation

1988-10-28

1991-04-16

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 25, 331 45, H03L 706, H03L 707

Patent

active

050086367

ABSTRACT:
A clock generation circuit on each circuit board of a computer system and which removes board-to-board system skew in clock signal distribution. A phase-locked loop is employed to maintain synchronization between the system reference clock signal distributed to each board and the outputs of the distribution gate array in the generation circuit on each board. A 2X frequency clock is provided by combining the clock signal with a delayed version of itself. A second order loop is employed to monitor the duty cycle of the 2X frequency clock and to adjust the duty cycle of the regular frequency clock to provide cycle-to-cycle symmetry for the 2X frequency clock.

REFERENCES:
patent: 3493884 (1970-02-01), Kulp
patent: 4021740 (1977-05-01), Horna
patent: 4185245 (1980-01-01), Fellinger et al.
patent: 4439689 (1984-03-01), Chazenfus
patent: 4754166 (1988-06-01), Nagano
IEEE Design & Test of Computers, vol. 5, No. 5, Oct. 1988, pp. 9-27: "Clock System Design", Wagner.

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