Apparatus for low-jitter frequency and phase locked loop and...

Details Apparatus for low-jitter frequency and phase locked loop and... Apparatus for low-jitter frequency and phase locked loop and...

2008-12-15

2010-11-02

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S00100A, C331S008000, C331S017000, C331S025000

Reexamination Certificate

active

07825737

ABSTRACT:
A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.

REFERENCES:
patent: 6542038 (2003-04-01), Nishimura et al.
patent: 6754147 (2004-06-01), Hsu et al.

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