Apparatus for logical simulation and method for producing logica

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364488, 395500, G06F 1560

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active

057966222

ABSTRACT:
In a logical synthesize design for an ASIC using a general purpose macro, to execute automatically retrieval/elimination of a redundancy function at a function level and to optimize the circuit precisely and speedily, a redundancy conditional statement retrieval unit 3 comprises a conditional statement retrieval unit 31 for retrieving a conditional statement to indicate a condition of an output versus an input from an input macro logical descriptive data; a state transition display descriptive addition unit 32 for producing an intermediate logical descriptive data to which a state transition data is added based on the retrieved conditional statement; a logical simulation unit 34 for executing a logical simulation of an operation mode control data and an input macro logical descriptive data to output status value data; an invariable conditional statement discrimination unit 36 for discriminating and extracting an invariable conditional statement having an invariable status value, based on the status value data; and an invariable conditional statement elimination unit 37 for eliminating the aforementioned invariable conditional statement from the input macro logical descriptive data based on the aforementioned discrimination result and for producing a new logical description.

REFERENCES:
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4816999 (1989-03-01), Berman et al.
patent: 5218557 (1993-06-01), Simoudis
patent: 5345393 (1994-09-01), Ueda
patent: 5657240 (1997-08-01), Chakradhar et al.

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