Apparatus for loading programmable hit matrices used in a hardwa

Details Apparatus for loading programmable hit matrices used in a hardwa Apparatus for loading programmable hit matrices used in a hardwa

1981-10-01

1984-07-03

Shaw, D. Gareth

Boots, shoes, and leggings

G06F 1130

Patent

active

044583095

ABSTRACT:
A data processing system includes a number of subsystems, all coupled in common to a system bus. Also coupled to the system bus is a hardware monitor interface unit (HMIU) for receiving all information transferred between subsystems. The HMIU includes programmable hit matrices (PHM's). The PHM's include memory circuits which generate "hit" signals when predetermined information addresses the memory circuits. The "hit" signals or binary ONE's are loaded into the memory circuits during a load mode during which system bus information specifically addressing the HMIU is received on two system bus cycles for each address location of the memory circuit. The data bus contains the memory circuit address during the first system bus cycle and the data during the second data bus cycle. An address bus signal identifies the cycle.

REFERENCES:
patent: 3284776 (1966-11-01), Freedman
patent: 3771141 (1973-11-01), Culler
patent: 4047244 (1977-09-01), Finkemeyer

Affiliated with

Also associated with

Rating

Apparatus for loading programmable hit matrices used in a hardwa does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for loading programmable hit matrices used in a hardwa, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for loading programmable hit matrices used in a hardwa will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1633507