Apparatus for limiting minority carrier injection in CMOS memori

Details Apparatus for limiting minority carrier injection in CMOS memori Apparatus for limiting minority carrier injection in CMOS memori

1984-02-17

1988-02-23

Moffitt, James W.

Static information storage and retrieval

Powering

357 51, G11C 1140

Patent

active

047275189

ABSTRACT:
A CMOS array is described where the memory cells are formed in n-type wells. No back biasing is employed. To prevent generation of minority carriers within the wells, on-chip filtering of power used for the devices in the wells and for biasing the wells is employed. Other techniques are used to reduce problems associated with minority carrier generation.

REFERENCES:
patent: 3974404 (1976-10-01), Davis
patent: 4139786 (1979-02-01), Raymond, Jr. et al.
patent: 4152627 (1979-05-01), Priel et al.
patent: 4323986 (1982-04-01), Malaviva
patent: 4367509 (1983-01-01), Snyder et al.

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