Electrical computers and digital processing systems: processing – Architecture based instruction processing
Reexamination Certificate
1993-11-12
2002-04-23
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
C712S214000, C712S215000, C712S220000, C712S227000
Reexamination Certificate
active
06378061
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to data processing systems and more particularly to an apparatus for issuing multiple instructions from sveral sources and in an order that ensures that the sources and destinations of the instructions do not collide with one another.
2. Description of the Related Art
Users of modern computers are demanding greater speed in the form of increased throughput (number of completed tasks per uinit of time) and increased speed (reduced time it takes to complete a task). The Reduced Instruction Set Computer (RISC) architecuture is one approach system designers have taken to achieve this. While there is no standard definition for the term Reduced Instruction Set Computer (RISC) as opposed to the usual computer architecture which can be called Complex Instruction Set Computer (CISC), there are some generally accepted characteristics of a RISC machine. Generally a RISC machine can issue and execute an instruction per clock. In a RISC machine only a very few instructions can access memory so most instructions use on-chip registers. So, a further RISC characterstic is the provision of a large number of registers on chip. In a RISC machine the user can specify in a single instruction two sources and a destination.
Having to fetch large numbers of instructions from off chip memory reduces bus bandwidth. When issuing multiple instructions from several sources on a machine bus, sometimes the destination operands of the instructions collide with one another resulting in a scoreboard hit condition. When this occurs in the prior art apparatus, the instruction is canceled and an additional fetch is required in order to reissue the instruction on the machine bus after a scoreboard hit is removed.
It is an object of the invention to provide an apparatus for issuing, on a machine bus, multiple instructions from several sources, for detecting if destination operands of the instructions collide with one another and for reissuing an instruction on the machine bus immediately after a collision condition related to that instruction is removed.
SUMMARY OF THE INVENTION
Briefly, the above objects are accomplished in accordance with the invention by providing instruction sequencer with a microcode translation ROM (
112
) for providing initial instructions in microcode flows and a mousetrap multiplexer (
104
) having a first input, a second input and an output. The first input of the mousetrap multiplexer (
104
) is connected to an instruction bus (
98
) and the the second input of the mousetrap multiplexer (
104
) is connected to the microcode translation ROM (
112
). The output of the mousetrap multiplexer (
104
) is connected to the machine bus (
110
). The mousetrap multiplexer (
104
) includes means for selecting at its inputs from one of either the instruction bus (
98
), or microcode translation ROM (
112
), an operand and an opcode field and for driving the selected operand and opcode field onto the machine bus (
110
).
The invention has the advantage of providing a superscaler architecture in that the machine can issue and execute more than one instruction per clock.
The invention has the advantage that since the microinstructions of the microcode are virtually identical to the RISC macroinstructions, a permanent cache of routines is stored on-chip that would be in most RISC machines have to come from off-chip.
The invention has the advantage that it is possible to issue two instructions per clock, which eliminates the bus bandwidth problems that would exist if all that code had to be fetched from off-chip.
REFERENCES:
patent: 4314349 (1982-02-01), Batcher
patent: 4388682 (1983-06-01), Eldridge
patent: 4394736 (1983-07-01), Bernstein et al.
patent: 4399505 (1983-08-01), Druke et al.
patent: 4591972 (1986-05-01), Guyer et al.
patent: 4635194 (1987-01-01), Burger et al.
patent: 4745544 (1988-05-01), Renner et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5101344 (1992-03-01), Bonet et al.
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5488714 (1996-01-01), Skidmore
patent: 5732234 (1998-03-01), Vassiliadis et al.
Yoshida “A Strategy for Avoiding Pipeline Interlock Delays in a Microprocessor” IEEE 1990, pp. 14-19.
Carbine Adrian
Hinton Glenn J.
Smith Frank S.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Dzung C
Pan Daniel H.
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