Apparatus for interrupt detection and arbitration

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Details

395325, 36424293, 364DIG1, 36493701, 364941, 364DIG2, G06F 1314, G06F 13368

Patent

active

052010511

ABSTRACT:
An apparatus for interrupt detection and arbitration in a system which includes a plurality of circuit modules connected to each other by a common bus line is disclosed. According to the present invention, within two bus cycles, it is possible for any interrupt source circuit modules to notify an arbitrated interrupt destination module directly, with a relatively low load being imposed on the CPUs in those circuit modules. An interrupt detector/arbiter circuit is provided in each of the circuit modules, and a central controller circuit is provided in the CPU module. The interrupt detector/arbiter circuits are assigned to corresponding bus lines and transfer the necessary interrupt information, such as the interrupt destination or the interrupt sources, by signals on the bus lines which correspond to the destination or source interrupt detector/arbiter circuits.

REFERENCES:
patent: 4365294 (1982-12-01), Stokken
patent: 4494192 (1985-01-01), Lew et al.
patent: 4608631 (1986-08-01), Stiffler et al.
patent: 4716523 (1987-12-01), Burrus, Jr. et al.
patent: 4870566 (1989-09-01), Cooper et al.

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