Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2000-04-05
2004-08-24
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S210000, C345S215000
Reexamination Certificate
active
06781581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a video signal generating apparatus, and more particularly to an apparatus for interfacing timing information in a digital display device.
2. Description of the Related Art
Hereinafter, a conventional apparatus for interfacing timing information in a digital display device is described with reference to the accompanying drawing.
FIG. 1
is a block diagram of an apparatus for interfacing timing information in a digital display device in accordance with the conventional art. Referring to
FIG. 1
, the apparatus includes; a video signal generating unit
1
for generating a video signal of R, G, and B and horizontal and vertical synchronizing signals of H and V; and a display unit
2
for recovering the video signal of R, G and B and the horizontal and vertical synchronizing signals generated from the video signal generating unit
1
to original signals and displaying the recovered signals on a display device
2
j.
The video signal generating unit
1
includes: a video signal generating part
1
a
for generating a video signal of R, G and B and horizontal and vertical synchronizing signals of H and V; and a first interfacing part
1
b
for interfacing a display information of the display unit
2
depending on a control signal of the video signal generating part
1
a
or a control processing unit (not shown).
The display unit
2
storing the display information includes: a second interfacing part
2
b
for interfacing the stored display information depending on an output signal of the video signal generating unit
1
; a video signal processing part
2
c
for transforming the video signal of R, G and B which is transmitted from the video signal generating unit
1
through a connector
2
a
to a video signal having a level corresponding to an input level of an analog/digital converting part
2
g
and outputting the level-transformed video signal; a synchronous signal processing part
2
d
for performing the polarity determination of the horizontal/vertical synchronous signal(H and V) which are transmitted from the video signal generating unit
1
through the connector
2
a
, the synchronous separation and the analysis of the synchronous signals; a MICOM
2
e
for analyzing a processing result of the synchronous signal processing part
2
d
, predicting timing information of the input video signals (R, G and B), and then outputting control signals corresponding thereto, thereby controlling whole operation of the system; a phase-locked loop
2
f
for generating a sampling clock of SC corresponding to the horizontal synchronous signal which is separated through the synchronous signal processing part
2
d
depending on the control signal of the MICOM
2
e
; an analog/digital converting part
2
g
for converting an analog video signal (ARGB) to a corresponding digital video signal (DRGB) to the analog video signal depending on the sampling clock SC of the phase-locked loop
2
f
; and a display signal converting part
2
h
for converting the digital video signal (DRGB) to be matched with an operational property of a display device
2
j
, which is converted by the analog/digital converting part
2
g.
The above constituted conventional timing information interfacing apparatus of the digital display device is described with reference to the accompanying drawing of FIG.
1
.
First, the video signal generating unit
1
generates a predetermined video signals(R, G and B) and horizontal/vertical synchronous signal (H and V). In other words, the video signal generating part
1
a
of the video signal generating unit
1
outputs a control signal to interface the display information of the display unit
2
. Here, the control signal for interfacing the display information may be applied directly by the CPU(not shown) to the first interfacing part
1
b.
The first interfacing part
1
b
interfaces the display information of the display unit
2
depending on the control signal of the video signal generating part
1
a
or a control signal of the CPU.
Accordingly, the video signal generating part
1
a
generates a predetermined video signals(R, G, B) adapted to the whole display information of the display unit
2
which has been interfaced through the first interfacing part
1
b.
Then, the display unit
2
recovers the video signals(R, G, B) and the horizontal/vertical synchronous signals output from the video signal generating unit
1
to the original signals and displays the recovered original video signal on the display device
2
j.
In other words, the second interfacing part
2
b
of the display unit
2
stores all the display information and interfaces the stored display information depending on the horizontal/vertical synchronous signal of the video signal generating unit
1
.
Thereafter, the video signal processing part
2
c
outputs the video signal of R, G and B which is transmitted from the video signal generating part
1
a
of the video signal generating unit
1
through the connector
2
a
and which is converted to correspond to the input level of the analog/digital converting part
2
g.
The synchronous signal processing part
2
d
performs the polarity determination of the horizontal/vertical synchronous signal(H and V) which are transmitted from the video signal generating unit
1
through the connector
2
a
, the separation of the synchronous signals and the analysis of the synchronous signals, and outputs the resultant signals.
Afterwards, the MICOM
2
e
analyze the signal processing result of the synchronous signal processing part
2
d
, predict the timing information of the input video signals(R, G, B), and then outputs a control signal corresponding thereto.
Then, the phase-locked loop
2
f
generates the sampling clock of SC corresponding to the horizontal synchronous signal which is separated through the synchronous signal processing part
2
d
depending on the control signal of the MICOM
2
e.
Accordingly, the analog/digital converting part
2
g
converts an analog video signal(ARGB) which has been processed in the video signal processing part
2
c
to a corresponding digital video signal(DRGB) to the analog video signal depending on the sampling clock SC of the phase-locked loop
2
f
, and outputs the converted digital video signal(DRGB).
Then, the display signal converting part
2
h
converts the digital video signal(DRGB) to be matched with an operational property of a display device
2
j
, which is converted by the analog/digital converting part
2
g
, and a third interfacing part
2
i
interfaces the converted digital video signal to display the interfaced digital video signal through the display device
2
j.
At this time, the MICOM
2
e
controls the sampling clock SC of the phase-locked loop
2
f
depending on the signal output from the display signal converting part
2
h.
The above sequences are repeatedly performed, to thereby display predetermined information to be employed to devices.
Thus, in the conventional timing information interfacing apparatus, the video signal generating unit outputs only video signal and synchronous signals while interfacing signals between the video signal generating unit and the display unit, and the display unit receives these video signal and synchronous signals, analyzes the synchronous signals provided from the video signal generating unit, and predicts the timing information of the video signal. Therefore, based on the predicted timing information value, any video information can be displayed.
The predicted timing information value is, however, inaccurate since the real timing information is different every video signal generating devices. Accordingly, it is essentially required to interface more accurate timing information.
And, in the conventional timing information interfacing apparatus, the MICOM analyzes the synchronous signals and predicts the timing information data to control the phase-locked loop. Here, the predicted timing information data differs from the timing information data used for making the original analog video signa
Dharia Prabodh M.
Edtech Co., Ltd.
Lee Hong Degerman Kang & Schmadeka
Shalwala Bipin
LandOfFree
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