Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2001-05-04
2002-08-13
Schuberg, Darren (Department: 2835)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S764000, C361S765000, C361S777000, C257S698000, C257S773000, C257S774000, C174S255000, C174S260000, C174S266000, C228S180210, C228S180220
Reexamination Certificate
active
06434016
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention pertains to the field of bus topologies. More particularly, the present invention pertains to an improved multiple load bus topology and associated circuit boards, systems, and methods.
2. Description of Related Art
The performance and cost of a circuit board in a multi-load topology are influenced by numerous design parameters. For example, routing between components on the circuit board, the placement of such components, and the types of vias used to interconnect different layers of routing in the circuit board all play an important role in determining the cost and performance of a circuit board. In the case of a circuit board intended for high-volume manufacturing, it may be advantageous to provide high performance while limiting overall cost; however, often high performance and low cost are conflicting goals.
Package routing refers to the routing of signal lines from pads of an integrated circuit to component pins. Pins are interconnect nodes that transfer signals from the component to circuit board traces and may take any of a variety of known or otherwise available forms (e.g., pins, solder balls, solder columns, etc.). Circuit board traces are signal lines as they are routed through one or more layers of the circuit board, and the bus length for a particular bus is the length of the traces that comprise the bus. As referred to herein, a stub offset is the distance on the bus between two connections to a single circuit board trace, and a chip offset is the horizontal distance in the plane of a circuit board between the midpoints of two devices mounted on the circuit board.
A typical circuit board may have numerous layers of traces within the circuit board to transmit signals from components mounted on both sides of the circuit board. Thus, trace routing is a complex three-dimensional problem which may be further complicated by the large number of pins densely populating modem components. Additionally, some systems may have design specific constraints such as a maximum trace length, or a requirement of some degree of consistency between trace lengths.
One prior art multi-load bus topology attaches devices to a bus arranged in a straight line on a single surface of a circuit board. As additional devices are added, such a bus necessarily becomes longer. At a certain point, the bus may be too long for signals to propagate between components within predetermined periods of time associated with proper bus operation. For example, in a system operating with a common bus clock between components, the bus may become too long for signals to propagate from end to end during a cycle of the common clock. In such cases, to provide operation at higher common clock frequencies, techniques that allow shortening of the bus may be required.
One prior art technique that shortens the total length of the bus is shown in
FIG. 1
a
. This prior art technique involves mounting devices on opposite sides of a circuit board in an overlapping manner. In
FIG. 1
a
, a device
155
is mounted on a first side of a circuit board
150
, and a device
160
is mounted on a second side of the circuit board
150
. Typically, many pins that need to be connected are not aligned. In cases where pins are aligned (e.g., pins
157
and
161
), a through-hole via
162
may be used to connect both pins to a signal line
164
at a single connection point
165
. Nonetheless, the connection of two stubs at a single connection point
165
may disadvantageously reduce signal quality when high frequency signaling is involved.
With respect to unaligned pins, expensive partial via techniques (e.g., blind and buried vias) may be needed to make the appropriate connections. For example, to connect pins
158
and
162
respectively from the device
155
and the device
160
to a signal line
170
, a partial via
166
and a partial via
174
respectively are used. Notably, the connection points
172
and
176
are spaced apart so that the stubs do not connect at a single point; however, the fully overlapping nature of devices
155
and
160
(i.e., being directly above/below each other) does not guarantee that a minimum stub offset can be maintained between pins. Therefore, disadvantages of this prior art approach may include the use of expensive vias and/or the inability to ensure minimum stub offsets.
Another prior art technique that allows mounting overlapping components on opposite sides of a circuit board is shown in
FIG. 1
b
(see also, e.g., U.S. Pat. No. 5,502,621). This technique also involves mounting a device
110
on a first side of a printed circuit board
105
and a device
135
on a second side of the printed circuit board
105
; however, the device
135
has corresponding pin positions in mirror image locations with respect to the device
110
. Corresponding pins are pins that are connected together in the system such as data bus pins
115
and
130
. In some systems, corresponding pins may be pins such as data bus pins (e.g., D
1
of device
1
is connected to D
1
of devices
2
,
3
, etc.), address bus pins, or certain control pins.
Due to the mirror image pin locations, simplified signal routing may be achieved because numerous corresponding pins from the device
110
and device
135
are directly opposite one another. For example, a pin
115
and a pin
130
may be connected together and to a signal line
140
at a single connection point
125
by a single through-hole via
120
. This technique, however, requires that a particular device be designed with multiple pin arrangements (standard and mirror image), thereby increasing the cost of manufacturing and maintaining inventory of the device. Additionally, both stubs connecting the devices
110
and
135
terminate at a single connection point
125
, which may undesirably reduce signal quality.
Accordingly, there is a continuing need to develop low cost and/or high speed circuit boards that maintain an appropriate signal level quality.
SUMMARY
A method and apparatus interconnecting multiple devices on a circuit board is disclosed. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.
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patent: 5982654 (1999-11-01), Corisis
patent: 5986893 (1999-11-01), Leigh et al.
patent: 5998864 (1999-12-01), Khandros et al.
patent: 0464113 (1992-02-01), None
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patent: 08102569 (1996-04-01), None
patent: WO 00/79850 (2000-05-01), None
Dabral Sanjay
Zeng Ming
Draeger Jeffrey S.
Foster David
Intel Corporation
Schuberg Darren
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