Apparatus for intelligent reduction of worst case power in memor

Details Apparatus for intelligent reduction of worst case power in memor Apparatus for intelligent reduction of worst case power in memor

1991-05-20

1993-10-19

Mottola, Steven

Static information storage and retrieval

Powering

365233, 365236, 365193, 365195, G11B 1730

Patent

active

052552411

ABSTRACT:
A memory system is implemented by an array of large scale integrated dynamic random access memory elements. The memory elements are of a type that permit data way word storage on a page basis, each page being defined on a row boundary. Discovering that excess power consumption by the memory can result from successive memory operations made back-to-back to different page locations, the present invention provides counter means to count each immediately successive different page memory operations so that, when that count matches a maximum count, memory operations are stalled for a period of time.

REFERENCES:
patent: 4280199 (1981-07-01), Osakabe et al.
patent: 4873666 (1989-10-01), Lefebvre et al.
patent: 4953128 (1990-08-01), Kawai et al.
patent: 4985868 (1991-01-01), Nakano et al.

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