Apparatus for inputting clock signal and data signals of...

Details Apparatus for inputting clock signal and data signals of... Apparatus for inputting clock signal and data signals of...

2005-05-11

2008-10-28

Tran, Khanh C (Department: 2611)

Pulse or digital communications

Receivers

Reexamination Certificate

active

07443926

ABSTRACT:
In an apparatus including a shift register adapted to pass a start signal therethrough in synchronization with a clock signal of a large amplitude level to sequentially generate a plurality of latch signals, a data register adapted to latch sequential data signals of the large amplitude level in synchronization with the latch signals, and a data latch circuit adapted to latch all the sequential data signals latched in the data register in synchronization with a strobe signal, a receiver converts differential clock signals of a small amplitude level into the clock signal of the large amplitude level from a timing of generation of the strobe signal to a timing of completion of latching all the sequential data signals in the data register, and transmits the clock signal of the large amplitude level to the shift register, and also, converts differential data signals of the small amplitude level into the sequential data signals from a timing of generation of the start signal to the timing of completion of latching all the sequential data signals in the data register and transmits the sequential data signals to the data register.

REFERENCES:
patent: 6097362 (2000-08-01), Kim
patent: 6166720 (2000-12-01), Sim
patent: 2002/0097208 (2002-07-01), Hashimoto
patent: 2003/0043129 (2003-03-01), Tazuke
patent: 2005/0146493 (2005-07-01), Kinjo et al.
patent: 11-249626 (1999-09-01), None

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