Patent
1994-03-31
1996-06-04
Downs, Robert W.
395 61, 395900, G06F 1518
Patent
active
055241743
ABSTRACT:
An apparatus for inference formation and defuzzification has an arithmetic unit, a memory/register unit, and a controller, wherein crisp output signals can be formed from weighting factors and dimensional scaling numbers dependent on control signals with a weighting factor being provided for each linguistic value of the output variables, the dimensional numbers characterizing the membership functions of the linguistic values of the output variables. The apparatus exhibits high processing speed and requires only low storage space, particularly given definitions of the crisp output signal of greater than or equal to eight bits.
REFERENCES:
patent: 5245695 (1993-09-01), Basehore
patent: 5371832 (1994-12-01), Eichfeld et al.
Patent Abstracts of Japan, vol. 4, No. 160 (P-035) for Japanese Patent Application 55108050.
"High Speed Multiplier," IBM Technical Disclosure Bulletin, vol. 13, No. 2, Jul., 1970 (pp. 546-548).
"An 8b Fuzzy Coprocessor for Fuzzy Control," Eichfeld et al., 1993 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb., 1993 pp. 180-181, 286.
"Parallel Dynamic Switching of Reasoning Methods in a Fuzzy System," Smith, Second IEEE International Conference on Fuzzy Systems, vol. II, pp. 968-973.
Eichfeld Herbert
Waidelich Markus
Downs Robert W.
Katbab A.
Siemens Aktiengesellschaft
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