Apparatus for implementing a block matching algorithm for motion

Television – Image signal processing circuitry specific to television – Motion vector generation

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348416, H04N 732

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active

058643729

ABSTRACT:
An apparatus for implementing block matching for motion estimation in video image processing. The apparatus receives the pixel data of an original image block and the pixel data of a compared image block selected from a number of compared image blocks during video image processing. The selected image blocks are compared to determine a movement vector. The apparatus has a multi-stage pipelined tree-architecture that includes four stages. The first computational stage produces corresponding pairs of difference data and sign data. A second compression stage in the process pipeline includes a compression array that receives all the difference data and sign data, which are added together to produce compressed summation data and compressed sign data. The third summation stage in the pipeline receives the compressed summation and sign data and produces a mean absolute error for the original and compared image block pixels. A last minimization stage receives the mean absolute error for each of the compared image blocks and determines a minimum mean absolute error from among them. The compression array includes of a number of full and half adders arranged in a multi-level configuration in which none of the adder operand inputs and the carry-in inputs is left un-connected.

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Li et al, "A New Three-Step Search Algorithm for Block Motion Estimation", IEEE Trans. on Circuits and Systems for Video Technology, vol. 4, No. 4, pp. 438-442 Aug. 1994.
Jehng et al, "An Efficient and Simple VLSI Tree Architecture for Motion Estimation algorithms", IEEE Trans. on Signal Processing, vol. 41, No. 2, pp. 889-900 Feb. 1993.
Gupta et al, "Architectures for Hierarchical and Other Block Matching Algorithms", IEEE Trans. on Circuits and Systems for Video Technology, vol. 5, No. 6, pp. 477-489 Dec. 1995.

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