Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2005-01-28
2009-10-06
Malzahn, David H (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07599979
ABSTRACT:
An apparatus and method for hybrid multiplication in GF(2m) by which trade-off between the area and the operation speed of an apparatus for a hybrid multiplier in finite field GF(2m) can be achieved are provided. The apparatus for hybrid multiplication includes: a matrix Z generation unit generating [m×k] matrix Z for performing a partial multiplication of a(x) and b(x), by dividing b(x) by k bits (k≦┌m/2┐), when multiplication of m-bit multiplier a(x) and m-bit multiplicand b(x) is performed from [(m+k−1)×k] coefficient matrix of a(x) in GF(2m); a partial multiplication unit performing the partial multiplication ┌m/k┐k−1 times in units of rows of the matrix Z to calculate an (┌m/k┐k−1)-th partial multiplication value and a final result value of the multiplication; and a reduction unit receiving the (┌m/k┐k−1)-th partial multiplication value fed back from the partial multiplication unit and performing reduction of the value in order to obtain a partial multiplication value next to the (┌m/k┐k−1)-th partial multiplication value.
REFERENCES:
patent: 4697248 (1987-09-01), Shirota
patent: 6044390 (2000-03-01), Golnabi et al.
patent: 7133889 (2006-11-01), Parthasarathy et al.
patent: 2002/0138534 (2002-09-01), Drescher
patent: 2003/0093450 (2003-05-01), Chen
patent: 2005/0033790 (2005-02-01), Hubert
patent: 1020010068349 (2001-07-01), None
Y.J. Choi et al., “Hybrid Multiplier for FG(2m) defined by some irreducible trinomials”, Electronics Letters, Jul. 8, 2004, vol. 40, No. 14 (pp. 852-853).
B. Sunar et al., Brief Contributions “Mastrovito Multiplier for All Trinomials”, IEEE Transactions on Computers, vol. 48, No. 5, May 1999 (pp. 522-527).
Chang Ku Young
Cho Hyun Sook
Choi Yong Je
Hong Do Won
Blakely , Sokoloff, Taylor & Zafman LLP
Electronics and Telecommunications Research Institute
Malzahn David H
LandOfFree
Apparatus for hybrid multiplier in GF(2 m ) and method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for hybrid multiplier in GF(2 m ) and method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for hybrid multiplier in GF(2 m ) and method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4122126