Excavating
Patent
1981-12-18
1984-06-26
Atkinson, Charles E.
Excavating
371 5, G01R 3128, G06F 1100
Patent
active
044569955
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
The invention generally relates to apparatus for mapping the faults of a large memory, at high memory speeds, and for classifying the mapped faults by types, wherein the memory comprises an array of semiconductor chips and accessed data words comprise bits from respective chips.
2. Background Art
U.S. Pat. No. 3,704,363, assigned to the present assignee, teaches the automatic collection of error statistical information, arising out of computer system use, the error information being classified as to the number of correctible errors encountered. The specific types of errors encountered, however, are not discoverable from the simple counts of the numbers of correctable and uncorrectable errors. That is, one can not deduce from the simple counts whether the individual errors are related to each other or not, and if so, what the relationship is.
U.S. Pat. No. 4,174,537 discloses another error logging technique wherein separate records are made of single bit and multiple bit errors encountered in reading out data from addressed, selected locations in memory but, again, no indication is produced as to any relationship existing between the individual errors.
U.S. Pat. No. 3,917,933 describes yet another error logging scheme which keeps an accounting of the number of correctible errors experienced in the same word group accessed from memory. An alerting signal is generated when a preset threshold number of correctible errors has occurred in the same word group so that preventive maintenance can be scheduled before an uncorrectible error occurs in that word group. However, no attempt is made to monitor the relationship, if any, between the individual detected errors.
DISCLOSURE OF INVENTION
The invention as claimed is directed to the classification of memory array faults in terms of the relationship therebetween, i.e., types or mechanisms of those faults. More particularly, a fault map is made of the memory by writing known data into the memory and by reading the data out in a predetermined sequence while comparing the output data with the known written data and counting the mismatches (errors). The sequence is selected so that the memory array is scanned first by successive word lines and then by successive bit lines within each of a plurality of chips. Based upon the number of errors encountered as the array is scanned, and upon the known direction of scan, a decision is made as to the type of fault, e.g., a failure of an entire bit line, a failure of an entire word line, a failure of the entire array, or a failure of only isolated bits.
Where the memory comprises an array of semiconductor chips and accessed data words comprise bits from different respective chips, means are provided for selecting a column of chips and then testing each chip in the selected column by sequentially scanning it first by word lines and then by bit lines. The errors are counted in one or more registers, which accumulate total fault count and the count of consecutive faults in the direction scanned. Fault type, i.e., the relationship (if any) between the individual faults detected, is deduced from the fault counts in the registers, taking into account the direction in which the respective chip was scanned to produce the given count. A status word is formed for each chip representing the deduced fault type.
The knowledge or fault type facilitates the electrical reconfiguration of the memory so that the faulty bits are scattered between the accessed data words in such a way that available error correcting capability can correct the remaining faulty bits in each data word. Without knowledge of the fault types, and in the presence of numerous faulty bits, memory reconfiguration can not be accomplished with desired efficiency. The high speed with which fault types are classified in accordance with the present invention permits the completion of fault mapping with only a brief interruption, on the order of minutes, to the normal operation of the system. A time saving of two orders of magnitude can be realiz
REFERENCES:
patent: 3659088 (1972-04-01), Boisvert, Jr.
patent: 3940601 (1976-02-01), Henry et al.
patent: 4039813 (1977-08-01), Kregness
patent: 4061908 (1977-12-01), de Jonge et al.
patent: 4066880 (1978-01-01), Salley
V. P. Srini, Fault Location in a Semiconductor Random-Access Memory Unit, IEEE Trans. on Computers, vol. C-27, No. 4, Apr. 1978, pp. 349-358.
D. J. Friend, Storage Checkout Method, IBM Technical Disclosure Bulletin, vol. 18, No. 3, Aug. 1975, pp. 930-932.
Atkinson Charles E.
Haase Robert J.
International Business Machines - Corporation
LandOfFree
Apparatus for high speed fault mapping of large memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for high speed fault mapping of large memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for high speed fault mapping of large memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2235295