Apparatus for high performance multiplication

Details Apparatus for high performance multiplication Apparatus for high performance multiplication

1988-04-01

1990-07-10

Harkcom, Gary V.

Boots, shoes, and leggings

364749, G06F 752

Patent

active

049411217

ABSTRACT:
A method and apparatus for performing high performance multiplication in a computer central processor unit which implements a sliced design configuration. Each slice changes its "personality" by virtue of receiving consecutive bits of the multiplicand. The receipt of consecutive bits by each slice eliminates the need for the interconnection of successive slices in separate chips. Thus, the apparatus allows the avoidance of significant timing delays, inherent in such interchip connections, which diminish computer system multiplication performance, and allows the multiply cycle time to be as fast as a latch-to-latch transfer across chips.

REFERENCES:
patent: 4130877 (1978-12-01), Rickers
patent: 4130878 (1978-12-01), Balph et al.
patent: 4224676 (1980-09-01), Appelt
patent: 4639857 (1987-01-01), McCanny et al.
patent: 4811269 (1989-03-01), Hirose et al.

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