Apparatus for handling out-of-order exceptions in pipe-lined par

Details Apparatus for handling out-of-order exceptions in pipe-lined par Apparatus for handling out-of-order exceptions in pipe-lined par

1992-04-03

1997-09-02

Lee, Thomas C.

Boots, shoes, and leggings

395382, 395383, 39518503, 395392, 395591, 395596, 3642318, 3649446, G06F 9302, G06F 938

Patent

active

056641389

ABSTRACT:
A parallel processing control apparatus comprises processing blocks each providing an equal function and incorporating pipeline operation units; a status register for storing statuses of the processing blocks; an instruction feeder for simultaneously allocating instructions to the processing blocks; a flagging unit for setting a flag for a corresponding one of the processing blocks to indicate that at least one instruction fed to another of the processing blocks and positioned, on a sequential model, behind an instruction being processed in the flagged processing block has been processed or passed through a specific stage; a flag holder for holding the flag; and a write controller for selecting a processing block whose status is to be written in the status register.

REFERENCES:
patent: 4750112 (1988-06-01), Jones et al.
patent: 4760519 (1988-07-01), Papworth et al.
patent: 4777593 (1988-10-01), Yoshida
patent: 4875160 (1989-10-01), Brown, III
patent: 4879676 (1989-11-01), Hansen
patent: 4893233 (1990-01-01), Denman et al.
patent: 4903264 (1990-02-01), Talgam et al.
patent: 4916652 (1990-04-01), Schwarz et al.
patent: 5051885 (1991-09-01), Yates, Jr. et al.
patent: 5075844 (1991-12-01), Jardine et al.
patent: 5109381 (1992-04-01), Duxbury et al.
patent: 5121486 (1992-06-01), Kurihara et al.
patent: 5193158 (1993-03-01), Kinney et al.
patent: 5193187 (1993-03-01), Strout, II et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5247628 (1993-09-01), Grohoski
patent: 5251306 (1993-10-01), Tran
patent: 5278840 (1994-01-01), Cutler et al.
patent: 5283874 (1994-02-01), Hammond
patent: 5297263 (1994-03-01), Ohtsuka et al.
patent: 5341482 (1994-08-01), Cutler et al.
patent: 5363495 (1994-11-01), Fry et al.
patent: 5375212 (1994-12-01), Saini
patent: 5379379 (1995-01-01), Becker et al.
IEEE Transactions on Computers, vol. c-33, No. 11, Nov. 1984, pp. 1013-1022, S. Weiss, et al., "Instruction Issue Logic Pipelined Supercomputers".

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