Apparatus for handling failures to provide a safe address transl

Details Apparatus for handling failures to provide a safe address transl Apparatus for handling failures to provide a safe address transl

1995-05-15

1997-11-04

Harvey, Jack B.

395825, 395413, 395401, G06F 300

Patent

active

056850115

ABSTRACT:
Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the first hardware means, and apparatus for handling a failure to provide an address translation.

REFERENCES:
patent: 5261057 (1993-11-01), Coyle et al.
patent: 5293622 (1994-03-01), Nicholson et al.
patent: 5347636 (1994-09-01), Ooi et al.
patent: 5353411 (1994-10-01), Nakaosa et al.

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