Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-06-27
2001-10-09
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000
Reexamination Certificate
active
06301189
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a synchronous memory device; and, more particularly, to an apparatus for generating write control signals applicable to double data rate SDRAM.
DESCRIPTION OF THE PRIOR ART
For achieving a high speed of operation in a dynamic random access memory (DRAM), synchronous DRAM (SDRAM) has been developed which operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM, and a double data rate (DDR) SDRAM.
In
FIG. 1
, there is shown a timing chart of a scheme of SDR SDRAM in a write mode.
As shown, when a write command is generated, the SDR SDRAM takes in one data in synchronization with rising edge of the external clock signal CLK, so that one data is processed during one period of the external clock signal CLK. Therefore, in order to achieve faster operating speed in the SDR SDRAM, an external clock speed should be increased. However, in that case, operating speed of memory device and other devices using the external clock signal should be also increased according to the increased external clock signal.
In
FIG. 2
, there is shown a block diagram of a write command decoder and units disposed on a data input path in a SDR SDRAM.
As shown, a write command decoder
300
receives write command signals from an external circuit. The write command signals include a chip select bar signal /CS, a row address strobe signal /RAS, a column address strobe bar signal /CAS, and a write enable bar signal /WE. The write command decoder
300
decodes the write command signals to generate internal write control signals, i.e., a CAS active signal ICASATV and a shield bar signal SHIELDB. The CAS active signal ICASATV is used to activate a data input path, and the shield bar signal SHIELDB is used to shield, or stop, a current write operation in response to an external interrupt.
A plurality of units such as buffer units
302
and
304
and latch units
306
and
308
, disposed on the data input path, are activated or inactivated in response to the internal write control signals. However, the shield bar signal SHIELDB should be inputted to all units using the CAS active signal ICASATV, resulting in an increase of chip size.
In
FIG. 3
, there is shown a timing chart of a scheme of DDR SDRAM in a write mode.
As shown, unlike the SDR SDRAM, the DDR SDRAM takes in two data in synchronization with both rising and falling edges of a data strobe signal DQS, which is different from an external clock signal CLK. As a result, the DDR SDRAM can process two data during one period of the external clock signal CLK, thereby increasing an operation speed.
For the scheme of the DDR SDRAM, additional write control signals are needed. However, there is problems that the conventional write command decoder shown in
FIG. 2
cannot apply to the DDR SDRAM, so that there is a demand for a write command decoder applicable to the data input path of the DDR SDRAM.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus for generating write control signals applicable to double data rate SDRAM.
In accordance with an aspect of the present invention, there is provided an apparatus for generating internal write control signals applicable to a double data rate SDRAM, comprising: a first means for receiving write command signals to generate a write standby signal and an initial column address strobe (CAS) active signal, wherein the write command signal includes a row address strobe (RAS) signal, a column address strobe (CAS) bar signal, a write enable (WE) bar signal, and a chip select (CS) bar signal; a second means for receiving the write standby signal to generate an input path enable signal; a third means for receiving the initial CAS (column address strobe) active signal to generate a write CAS active signal and a write shield bar signal; a fourth means for receiving the write command signals and the write shield bar signal to generate a precharge shield bar signal and a read shield bar signal, wherein the precharge shield bar signal is fed back to an input terminal of the fourth means and is inputted as another input signal of the second means; and a fifth means for receiving the write shield bar signal and the read shield bar signal to generate an internal CAS active signal.
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Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Nelms David
Tran M.
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