Apparatus for generating self-timing for on-chip cache

Details Apparatus for generating self-timing for on-chip cache Apparatus for generating self-timing for on-chip cache

1990-04-06

1991-07-09

Clawson, Jr., Joseph E.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518907, 365233, G11C 1504

Patent

active

050311417

ABSTRACT:
A circuit for generating timing signals for operating an on-chip cache memory in which read operations of the cache memory occur in a first phase of a clock cycle and while operations occur in a second phase of the clock cycle and in which the operations to be accomplished in the second phase require a time for performance which may exceed the length of the second phase comprising means for generating the beginning of a write select signal as soon after the occurrence of both a write pulse and a hit signal as possible, and means for terminating the write select signal after a delay initiated by second phase of the clock cycle and termianted after a time sufficient to allow a write to take plate which time may actually extend into the next phase of the clock cycle.

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patent: 4794567 (1988-12-01), Akatsuka
patent: 4833642 (1989-05-01), OOi
patent: 4872138 (1989-10-01), Ciacci
patent: 4926384 (1990-05-01), Roy
patent: 4945512 (1990-07-01), Pekarske et al.
patent: 4953129 (1990-08-01), Kobayashi et al.

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