Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2003-08-26
2004-10-05
Young, Brian (Department: 2819)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S120000, C327S258000
Reexamination Certificate
active
06801066
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a data recovery circuit, and more particularly to a controllable quadrature phase generator in a half-rate data recovery circuit for generating two clock signals that are 90 degrees out of phase with each other.
2. Description of the Related Art
In digital data processing, all digital data is clocked by an associated clock signal, the period of which is equal to that of the digital data, so that a digital circuit is allowed to process digital data and to function properly. When digital data is transmitted serially, the associated clock signal is not transmitted along with the digital data for the consideration of transmission efficiency. Therefore, the receiving end must be able to extract clock signal from the incoming data so that the received data can be correctly recovered. Phase locked loop (PLL) circuits are generally used in circuits for data recovery.
FIG. 1
shows a schematic block diagram of a conventional data recovery circuit. As shown, a data recovery circuit
10
mainly comprises a clock source
12
, a phase detector
14
and a loop filter
16
. The clock source
12
is for example a voltage-controlled oscillator for generating a reference clock signal CLK having the same frequency as the incoming data signal. The phase detector
14
compares the phase of the incoming data signal to the phase of the reference clock signal CLK, determining whether or not these two signals are synchronous with each other. If the incoming data signal leads or lags the reference clock signal CLK, then the phase detector
14
generates a phase error signal which is a function of the phase difference between these two signals. The phase error signal is then applied to the loop filter
16
so as to eliminate the undesired high frequency noise and to output a control signal for feedback to the clock source
12
. The clock source
12
is controlled based on the control signal to adjust the phase of the reference clock signal CLK. In this way, the reference clock signal CLK can be synchronized with the incoming data signal and thus may be used for retiming the incoming data signal to thereby produce the correctly recovered data.
Recently, the demand for higher transmission speed has been rapidly increasing. However, the maximum data rate allowed by the phase detector in the above full-rate data recovery circuit is approaching the limit. Therefore, such circuit can hardly satisfy the speed demand in high speed serial communication. A half-rate data recovery circuit has been developed to solve this issue. This half-rate data recovery circuit, which operates at a frequency equal to half the rate of the incoming data stream, approximately doubles the maximum data rate allowed to be processed by the circuit at the receiving end.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an apparatus for generating two quadrature clock signals, i.e., two clock signals being 90 degrees out of phase with each other, by using a plurality of reference clock signals. The phase of the generated clock signals can be digitally controlled and adjustable through the whole cycle.
Another object of the present invention is to provide a half-rate data recovery circuit using the above apparatus for generating two quadrature clock signals being 90 degrees out of phase with each other and having a frequency equal to half the incoming data rate.
To achieve the above objects, according to one aspect of the present invention, an apparatus for generating quadrature phase signals comprises a base selector, a first phase interpolator and a second phase interpolator. The base selector generates a first, a second, a third and a fourth base clock signals in accordance with a region control signal by using a plurality of reference clock signals of the same frequency and different phases. The first and the second base clock signals are used as boundaries for defining a phase region for a first clock signal while the third and the fourth base clock signals are used as boundaries for defining a phase region for a second clock signal. The phase difference between the first and the second base clock signals is substantially equal to the phase difference between the third and the fourth base clock signals, and the phase difference between the first and the third base clock signals and the phase difference between the second and the fourth base clock signals are both substantially 90 degrees. The first phase interpolator operates in accordance with a position control signal to generate a first clock signal, the phase of which is a weighted average of the phases of the first and the second base clock signals. Similarly, the second phase interpolator operates in accordance with the same position control signal to generate a second clock signal, the phase of which is a weighted average of the third and the fourth base clock signals. The first and the second clock signals both have the same frequency and are substantially 90 degrees out of phase with each other.
According to another aspect of the present invention, a data recovery circuit is designed to incorporate the above apparatus for generating two quadrature clock signals including a first and a second clock signals having a frequency equal to half the frequency of an incoming data signal received by the data recovery circuit. The clock signals are fed into a phase detector for phase comparison with the incoming data, which in turn generates a phase error signal. A digital loop filter operates on the basis of the phase error signal to digitally control the apparatus for generating two quadrature clock signals, adjusting the phases of the generated clock signals so that the second clock signal is synchronous with the incoming data signal and the first clock signal is always maintained 90 degrees out of phase with the second clock signal.
REFERENCES:
patent: 5554945 (1996-09-01), Lee et al.
patent: 6122336 (2000-09-01), Anderson
patent: 6564359 (2003-05-01), Saeki
patent: 6570944 (2003-05-01), Best et al.
Bednarek Michael D.
MStar Semiconductor Inc.
Nguyen John B
Shaw Pittman LLP
Young Brian
LandOfFree
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