Apparatus for generating memory-internal command signals...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S189110, C365S189120, C365S191000, C365S230060

Reexamination Certificate

active

06704243

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of memory systems and in particular to the field of means for generating memory-internal command signals for memory systems.
2. Description of the Related Art
In memory systems, like for example a DRAM memory (DRAM=dynamic random access memory) typically several subprocesses have to be carried out in the memory system for performing a memory operation, as for example a read operation, a write operation or an update operation. Such subprocesses for example include an activation of a memory bank, an activation of row address lines, an activation of a read process or a write process or a precharging, in order to bring the memory system for the next memory operation into an available state.
These processes need to be performed with delays time matched to each other, in order to avoid conflicts resulting from a too early or too late triggering of the processes.
Typically, a command decoder is used for controlling these time matched storage processes, which is connected to a command line, like for example a command bus line, on the input side for receiving memory operation commands and connected to internal command signal lines of the memory system on the output side for outputting commands associated with the respective subprocesses.
The command for performing a memory operation is thereby applied to the input of the command decoder via the command line, wherein the command decoder thereupon creates one or several memory-internal command signals which are applied to internal command signal lines of the memory system.
FIG. 1
shows a known command decoder, wherein one command input
110
is connected to several delay units
112
a,
112
b,
112
c.
Each of the delay units
112
a,
112
b
and
112
c
is connected to a first input of the AND logic elements
116
a,
116
b,
116
c,
respectively, via the signal lines
114
a,
114
b,
114
c,
respectively.
Second inputs of the AND logic elements
116
a
-
116
c
are further connected to a clock signal input
120
via a signal line
118
. Furthermore, the outputs of the AND logic elements
116
a
-
116
c
are connected to memory-internal command signal lines
122
a,
122
b,
122
c,
respectively. In the known command decoder according to
FIG. 1
a memory-internal ACTIVATE command signal is transmitted via the command signal line
122
a,
a memory-internal WRITE command signal is transmitted via the command signal line
122
b
and a memory-internal PRECHARGE command signal is transmitted via the command signal line
122
c.
A command is input to the command input
110
via a command line, wherein the command causes the delay units
112
a
-
112
c
to be activated. The delay units
112
a
-
112
c
thereby are implemented such that a respective delay unit generates an output signal at the outputs
114
a
-
114
c
after a respective time period T1, T2 and Tn associated with it, with respect to the time or points of time of applying the command to the command input
110
. This is performed in that a delay unit, for example delay unit
112
a
pulls or sets the output line associated with it, i.e. line
114
a
in the above example, from a logical low state to a logical high state.
The output signals are applied to the first inputs of the AND logic elements
116
a
-
116
c
via the signal lines
114
a
-
114
c.
Thereafter, AND-operations with an external clock signal, i.e. more precisely with a state of the line
118
which is determined by the external clock signal, are performed in the AND logic elements
116
a
-
116
c.
The clock signal is thereby applied to the line
118
connected to the respective second inputs of the logic elements
116
a
-
116
c
via the clock signal input
120
.
The AND-operation to the external clock signal causes that the time-delayed output signals of the delay units
112
a
-
112
c
are time-synchronized with the external clock signal, so that time-delayed memory-internal command signals are generated at the outputs of the AND logic elements
116
a
-
116
c
which are time-matched to one of the signal edges of the external clock signal, i.e. either to the rising edge of the external clock signal or the falling edge of same.
The delay values T1, T2, Tn, respectively, of the time delay units
112
a
-
112
c
are each determined according to the command signals generated by same. By the delay unit
112
, for example, a time delay for an activate command signal is determined, wherein the time delay T1 is selected depending on the time at which the memory-internal ACTIVATE command signal is to be applied via the command signal line
122
a
of the memory system. Accordingly, the delay value T2 of the delay unit
112
b
is determined such that between the memory-internal WRITE command signal output at the command signal line
122
and the ACTIVATE command signal output at the command signal line
122
a
such a time delay results, which securely allows the memory system to be able to carry out a write action to the same after activating one or several memory cells of the memory system.
Consequently, the delay time values T1, T2, Tn need to be preset considering the type and the way of functioning of the memory system to which the known command decoder is connected, so that the processes triggered by the command signals are performed in the memory system without conflicts.
The selection of the delay values T1, T2, Tn, respectively, thereby needs to ensure, that at the time at which the command signal is applied to the memory system via the command signal lines
122
a
-
122
c,
the memory system is ready to properly perform the process caused by the command signal at the memory system.
It is thereby disadvantageous that the performance of the memory systems may be slightly different from memory chip to memory chip. These fluctuations of the performance are caused by fluctuations of parameters in the manufacturing process and include, for example, fluctuations of the width of metallic conductor tracks, different dopant concentrations, etc. This results in different optimum times for generating a respective memory-internal command signal for each memory system.
It is therefore desirable for a certain memory system to generate the command signals close to the optimum time for each respective memory system in order to prevent excessive delays between successive command signals which might result in a bad performance and excessive operation times for performing the memory operation.
The known command decoder according to
FIG. 1
thereby has the disadvantage that the delay units
112
a
-
112
c
generate the respective delays asynchronous with the external clock signal. This means, that the time at which a respective line
114
a
-
114
c
is set to a logical high state by the delay unit
112
a
-
112
c
associated with it is not time-matched to the time, at which the clock signal line
118
is set to a logical high state by the external clock signal.
If, for example, the line
114
a
is pulled to a logical high state at a time shortly after the clock signal line
118
has been pulled to a logical low state, then the memory-internal command signal is only generated to a logical high state with the next transition of the clock signal line
118
, i.e. about one clock period later. Consequently, it is not possible with the known command decoder to achieve a high time accuracy of generating the memory-internal clock signals.
Furthermore, it is not possible with the known command decoder to set and/or program the time of generating the memory-internal command signals. A settable delay is desirable, as the performance of the memory system may differentiate from chip to chip, as was mentioned above.
Additionally, with the known command decoder it is difficult to carry out a characterization, i.e. to determine which delays are optimum for the present memory chip. In order to carry out such a characterization of memory timing parameters, like for example a writeback, in the known command decoder, test methods need to be used in which the m

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