Apparatus for generating memory address of a display memory

Details Apparatus for generating memory address of a display memory Apparatus for generating memory address of a display memory

1987-02-17

1988-10-18

Birmiel, Howard A.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340724, 340730, 340747, G09G 116

Patent

active

047790849

ABSTRACT:
A memory address signal for a display memory is generated from a memory address generating circuit. The memory address generating circuit has an offset register and a memory address counter in addition to a memory address register. The offset register stores an offset value corresponding to a difference between a width of the display memory and a width of a display picture in a scanning direction. The memory address counter counts up a character clock in order to deliver the memory address signal after loading a start address of each horizontal scanning line of the display picture. At the end of each horizontal scanning line, an adder adds the offset value to the memory address signal. The addition thereof is loaded into the address register as the start address of the next horizontal scanning line.

REFERENCES:
patent: 4356482 (1982-10-01), Oguchi
patent: 4364037 (1982-12-01), Walker
patent: 4368466 (1983-01-01), Dwire
patent: 4688033 (1987-08-01), Carini et al.

Affiliated with

Also associated with

Rating

Apparatus for generating memory address of a display memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for generating memory address of a display memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for generating memory address of a display memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1197342