Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-06-26
2001-09-11
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000
Reexamination Certificate
active
06288971
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a synchronous memory device; and, more particularly, to an apparatus for generating a data strobe signal applicable to a double data rate SDRAM.
DESCRIPTION OF THE PRIOR ART
For achieving a high speed of operation in DRAM (dynamic random access memory), synchronous DRAMs (hereinafter, referred to as SDRAMs) have been developed. The SDRAM operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM and a double data rate (DDR) SDRAM and the like.
The SDR SDRAM operates in synchronization with rising edges of the external clock, so that one data is processed within one period of the external clock. On the contrary, the DDR SDRAM operates in synchronization with rising and falling edges of a data strobe signal, so that two successive data are processed within one period of the external clock. Therefore, compared with the SDR SDRAM, the DDR SDRAM achieves at least twice the operation speed without increasing a frequency of the external clock. At this time, the data strobe signal is a signal instructing reception of a data to a controller.
FIG. 1
is a timing chart illustrating a data strobe signal generator shown in
FIG. 2
at a read operation in case here a burst length is of 2 and a CAS (column address strobe) latency is of 2.5.
Two data DQ are continuously outputted within one period of an external clock signal CLK, being synchronized with rising and falling edges of the data strobe signal DQS. When a read command is inputted, the data strobe signal DQS maintains a high impedance state. Then, the data strobe signal DQS does not becomes a logic low state until one and half period of the external clock CLK elapses from the input of the read command. That state is called a “preamble” state when the data strobe signal DQS is in a logic low state before the data DQ is outputted.
If the data DQ is outputted, the data strobe signal DQS is synchronized with a first output data so that the data strobe signal DQS goes from the preamble state to a logic state. With the next data output, the data strobe signal DQS goes from the logic high state to a logic low state. If successive data are outputted when the burst length is of more that two, the data strobe signal DQS is toggled according to a transition from the logic high state to a logic low state, or vice versa.
When the data output has been completed, the data strobe signal DQS goes again to the high impedance state, informing to an external circuit that there is not data output any longer. At this time, that state is called a “postamble” state when the data strobe signal DQS is in a logic low state before the data strobe signal DQS again becomes the high impedance state.
At this time, a data strobe enable signal QSEN and a data strobe preamble control signal QSEN_PRE are used to control the data strobe signal DQS.
FIG. 2
is a schematic diagram illustrating a conventional data strobe signal generator
200
with preamble control portion
202
, signal generating portion
204
, and signal driving portion
208
, with the signal generating portion
204
including a plurality of pairs
206
A,
206
B,
216
A,
216
B,
226
A,
226
B of pull-up/pull-down signal drivers.
FIG. 3
is a circuit diagram illustrating a pull-up/pull-down signal driver
206
shown in FIG.
2
.
A structure and operation of the data strobe signal generator
200
and the pull-up/pull-down signal driver is disclosed in a copending U.S Pat. Ser. No. 475,056, filed on Dec. 30, 1999, entitled “DATA STROBE SIGNAL GENERATOR OF SEMICONDUCTOR DEVICE USING TOGGLED PULL-UP AND PULL-DOWN SIGNALS”, which is hereby incorporated by reference.
As shown in
FIG. 3
, it should be noted that each of the pull-up/pull-down signal drivers
206
includes inverters INV
31
to INV
34
for buffering a pull-up signal PU and a pull-down signal PD. That is, in the conventional data strobe signal generator
200
, when the pull-up signal PU and the pull-down signal PD are fed back, the pull-up signal PU and the pull-down signal PD are buffered through two inverters INV
31
and INV
32
, INV
33
and INV
34
, respectively. Therefore, junction capacitance looking from a pull-up node N
pu
and a pull-down node N
pd
may be increased, so that an operation speed is reduced. Additionally, as the number of the pipe counter signals PCNT, e.g., PCNT_EVEN<
0
:
2
> and PCNT_ODD<
0
:
2
>, increases, the junction capacitance at the pull-up node N
pu
and the pull-down node N
pd
may be increased much more.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus for generating a data strobe signal applicable to a double data rate SDRAM, capable of obtaining a stable operation speed regardless of the number of successive output data and reducing a chip size.
It is an aspect of the present invention to provide a 1. A synchronous memory device having an apparatus for generating a data strobe signal, the apparatus for generating a data strobe signal comprising: a preamble control means for controlling a preamble state of a data strobe signal in response to a data strobe preamble control signal; at least one pair of pull-up/pull-down signal generating means coupled to the preamble control means, for receiving pipe counter signals at a first input terminal to generate pull-up and pull-down signals; a common pull-up signal buffering means for buffering the pull-up signal to generate a buffered pull-up signal, wherein the buffered pull-up signal is commonly inputted to a second input terminal of the pull-up/pull-down signal generating means; a common pull-down signal buffering means for buffering the pull-up signal to generate a buffered pull-down signal, wherein the buffered pull-down signal is commonly inputted to a third input terminal of the pull-up/pull-down signal generating means; and a data strobe signal driving means for outputting the data strobe signal in response to the pull-up signal, the pull-down signals and a data strobe enable signal.
REFERENCES:
patent: 6011751 (2000-01-01), Hirabayashi et al.
patent: 6052329 (2000-04-01), Nishino et al.
Ho Hoai V.
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
LandOfFree
Apparatus for generating data strobe signal applicable to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for generating data strobe signal applicable to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for generating data strobe signal applicable to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2455982