Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
Patent
1998-03-12
2000-11-14
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Instruction decoding
Predecoding of instruction component
712215, 712217, G06F 930, G06F 928
Patent
active
061483931
ABSTRACT:
A valid mask generator comprising a series of mask generation blocks. Each block generates a predetermined number of valid mask bits given a predetermined number of start pointer bits and end bits, wherein said predetermined number of valid mask bits generated by each block is less than the total number of bits in the valid mask. The series of mask generation blocks may be connected in series, wherein each block outputs a carry-out signal, and wherein each block receives the carry-out signal from the node before it as a carry-in signal. A method for generating a valid mask from a start pointer and a plurality of end bits is also contemplated.
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Narayan Rammohan
Southard Shane
Tran Thang M.
Advanced Micro Devices , Inc.
An Meng-Ai T.
Chang J.
Christen Dan R.
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