Apparatus for furnishing instructions in a microprocessor with a

Boots – shoes – and leggings

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395800, 3642318, 3642613, 364DIG1, G06F 932

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active

054540909

ABSTRACT:
An apparatus for furnishing instructions having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, includes a memory; an address register having contents pointing to an instruction to be processed in said memory; an instruction register for receiving a loading of the instruction during an instruction loading phase; an arithmetic calculation unit for calculating addresses; an incrementing stage for incrementing the contents of said address register; and a multiplexer for selecting a calculated address or an incremented successor address. One embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit. Another embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit.

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Elektronik vol. 2, Jan. 19, 1990 (Nissen et al.) pp. 46-56.

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