Apparatus for frequency dividing a master clock signal by a...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

Reexamination Certificate

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C327S117000

Reexamination Certificate

active

07034584

ABSTRACT:
A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.

REFERENCES:
patent: 5371417 (1994-12-01), Mirov et al.
patent: 5528181 (1996-06-01), Suggs
patent: 6570417 (2003-05-01), Choi et al.
patent: 6707327 (2004-03-01), Choi et al.
patent: 6809567 (2004-10-01), Kim et al.
patent: 6882190 (2005-04-01), Choi et al.

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