Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2005-10-31
2008-08-19
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S113000, C438S114000, C438S460000, C438S462000, C438S465000
Reexamination Certificate
active
07413927
ABSTRACT:
An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material. When the die is mounted to a substrate, the additional underfill material in the recess regions helps form more robust fillets than otherwise possible.
REFERENCES:
patent: 5008189 (1991-04-01), Oroskar et al.
patent: 5128746 (1992-07-01), Pennisi et al.
patent: 5136365 (1992-08-01), Pennisi et al.
patent: 5214308 (1993-05-01), Nishiguchi et al.
patent: 5244143 (1993-09-01), Ference et al.
patent: 5250843 (1993-10-01), Eichelberger
patent: 5329423 (1994-07-01), Scholz
patent: 5376403 (1994-12-01), Capote et al.
patent: 5495439 (1996-02-01), Morihara
patent: 5500534 (1996-03-01), Robinson et al.
patent: 5587342 (1996-12-01), Lin et al.
patent: 5668059 (1997-09-01), Christie et al.
patent: 5698894 (1997-12-01), Bryant et al.
patent: 5736456 (1998-04-01), Akram
patent: 5767010 (1998-06-01), Mis et al.
patent: 5768290 (1998-06-01), Akamatsu
patent: 5773359 (1998-06-01), Mitchell et al.
patent: 5872633 (1999-02-01), Holzapfel et al.
patent: 5880530 (1999-03-01), Mashimoto et al.
patent: 5895976 (1999-04-01), Morrell et al.
patent: 5925936 (1999-07-01), Yamaji
patent: 5937320 (1999-08-01), Andricacos et al.
patent: 5953623 (1999-09-01), Boyko et al.
patent: 5977632 (1999-11-01), Beddingfield
patent: 6023094 (2000-02-01), Kao et al.
patent: 6060373 (2000-05-01), Saitoh
patent: 6063647 (2000-05-01), Chen et al.
patent: 6071757 (2000-06-01), Fogal et al.
patent: 6100114 (2000-08-01), Milkovich et al.
patent: 6121689 (2000-09-01), Capote et al.
patent: 6130473 (2000-10-01), Mostafazadeh et al.
patent: 6171887 (2001-01-01), Yamaji
patent: 6190940 (2001-02-01), Defelice et al.
patent: 6228678 (2001-05-01), Gilleo et al.
patent: 6245595 (2001-06-01), Nguyen et al.
patent: 6258626 (2001-07-01), Wang et al.
patent: 6288444 (2001-09-01), Abe et al.
patent: 6297560 (2001-10-01), Capote et al.
patent: 6307269 (2001-10-01), Akiyama et al.
patent: 6316528 (2001-11-01), Iida et al.
patent: 6327158 (2001-12-01), Kelkar et al.
patent: 6346296 (2002-02-01), McCarthy et al.
patent: 6352881 (2002-03-01), Nguyen et al.
patent: 6358627 (2002-03-01), Benenati et al.
patent: 6372547 (2002-04-01), Nakamura et al.
patent: 6391683 (2002-05-01), Chiu et al.
patent: 6429238 (2002-08-01), Sumita et al.
patent: 6455920 (2002-09-01), Fukasawa et al.
patent: 6479308 (2002-11-01), Eldridge
patent: 6486562 (2002-11-01), Kato
patent: 6507118 (2003-01-01), Schueller
patent: 6605479 (2003-08-01), Pasadyn et al.
patent: 6649445 (2003-11-01), Qi et al.
patent: 6683379 (2004-01-01), Haji et al.
patent: 6791194 (2004-09-01), Nagai et al.
patent: 6818550 (2004-11-01), Shibata
patent: 6822324 (2004-11-01), Tao et al.
patent: 2002/0003299 (2002-01-01), Nakamura et al.
patent: 2002/0014703 (2002-02-01), Capote et al.
patent: 2002/0027257 (2002-03-01), Kinsman et al.
patent: 2002/0031868 (2002-03-01), Capote
patent: 2002/0109228 (2002-08-01), Buchwalter et al.
patent: 2002/0171152 (2002-11-01), Miyazaki
patent: 2003/0001283 (2003-01-01), Kumamoto
patent: 2003/0013233 (2003-01-01), Shibata
patent: 2003/0080360 (2003-05-01), Lee et al.
patent: 2003/0087475 (2003-05-01), Sterrett et al.
patent: 2003/0099767 (2003-05-01), Fang
patent: 2003/0127502 (2003-07-01), Alvarez
patent: 2003/0129789 (2003-07-01), Smith et al.
patent: 2003/0169064 (2003-09-01), Pirkle et al.
patent: 2003/0193096 (2003-10-01), Tao et al.
patent: 2003/0218258 (2003-11-01), Charles et al.
patent: 2004/0002181 (2004-01-01), Scheifers et al.
patent: 2005/0516331 (2005-07-01), Akram
patent: 2005/0212142 (2005-09-01), Miyazaki et al.
Nguyen et al. Patent Application Entitled “Method and Apparatus for Forming an Underfill Adhesive Layer”, U.S. Appl. No. 10/080,913, filed Feb. 21, 2002.
Nguyen et al., “Effect of Underfill Fillet Configuration on Flip Chip Package Reliability”, SEMI® Technology Symposium: International Electronics Manfacturing Technology (IEMT) Symposium, SEMICON® West 2002.
“Flip Chip Products, Polymer Collar™ Wafer Level Package, Polymer Collar Overview”, www.kns.com, downloaded Jan. 23, 2003.
“Flip Chip Products, Polymer Collar™ Wafer Level Package, See the Polymer Collar™ WLP Difference!”, www.kns.com, downloaded Jan. 23, 2003.
Lau et al., “Solder-Bumped Flip Chip and Wire-Bonding Chip on CSP Substrate”, Chip Scale Package, Design, Materials, Process, Reliability, and Applications, Chapter 1, pp. 1-41.
Morris et al., Fundamentals of Microsystems Packaging, Chapter 2, pp. 44-79, Chapter 10, pp. 398-418, Chapter 17, pp. 658-693.
Office Action mailed Aug. 4, 2005 in U.S. Appl. No. 10/224,291.
“Polymer Collar WLP™, Wafer Level Package Family”, © 2002, downloaded from www.kns.com/prodserv/PDFS/FCD/polymer—collar.pdf, 2 pages.
“Presenting Polymer Collar WLP™—A New Wafer Level Package for Improved Solder Joint Reliability”, © 2002, downloaded from www.kns.com/prodserv/flipchip/pdf/PC—ad.pdf, 1 page.
Barrett et al., Kulicke & Soffa, “Polymer Collar WLP™—A New Wafer Level Package for Improved Solder Joint Reliability”, © 2002, downloaded from www.kns.com/resources/articles/PolymerCollar.pdf. 9 pages.
Bogatin, Eric, “All Dressed Up and Nowhere to Go”; Semiconductor International, May 1, 2002, downloaded Dec. 23, 2003, from www.reed-electronics.com/semiconductor/index.asp?layout=article@articleid=CA213812@rid=0&rme=0&cfd=1, 2 pages.
Kelkar Nikhil
Nguyen Hau T.
Patwardhan Viraj A.
Beyer Law Group LLP
Duong Khanh B
National Semiconductor Corporation
Smith Zandra
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