Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2007-11-27
2007-11-27
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S622000, C257S778000, C438S108000, C438S127000
Reexamination Certificate
active
10366067
ABSTRACT:
An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the integrated circuit die being separated by scribe lines on the wafer. Once the circuitry has been fabricated, grooves are formed along the scribe lines on the first surface of the semiconductor wafer. The first surface of the semiconductor wafer is then covered with a layer of underfill material, including within the grooves formed along the scribe lines on the first surface of the semiconductor wafer. After the wafer is singulated, the resulting die includes a first top surface and a second bottom surface and four side surfaces. Integrated circuitry is formed on the first surface of the die. Recess regions created by cutting the grooves are formed on all four side surfaces of the die and filled with the underfill material. When the die is mounted to a substrate, the additional underfill material in the recess regions helps form more robust fillets than otherwise possible.
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Kelkar Nikhil
Nguyen Hau T.
Patwardhan Viraj A.
Beyer & Weaver, LLP
Duong Khanh
National Semiconductor Corporation
Wilczewski Mary
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