Apparatus for finding quotient in a digital system

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364761, G06F 752

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active

054167337

ABSTRACT:
A fast divider is disclosed in the present invention. It utilizes a division method which uses a smaller quotient digit set of {-1, 1} than {-1, 0, 1} that used by known algorithms, therefore accelerates the speed of calculation. Partial remainders are computed with the signs of remainders decided independently and in parallel. By taking the absolute values of the remainders, the remainders are successively subtracted without the need of knowing the signs of remainders, while signs of the remainders can be decided in parallel and independently at the same time. The method adopts non-restoring division operation and CSA (carry save adder) type of operation for fast subtraction. The method is also an on-line algorithm that facilitates highly pipelined operations while it is much simpler than the existing on-line algorithms.

REFERENCES:
patent: 4866655 (1989-09-01), Nishiyama et al.
patent: 4873660 (1989-10-01), Nishiyama et al.
patent: 4878192 (1989-10-01), Nishiyama et al.
patent: 4935892 (1990-06-01), Nishiyama et al.
Tung, "Division Algorithm for Signed-Digit Arithmetic" IEEE Trans. on Computers Sep. 1968, pp. 887-889.

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