Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – With measuring – sensing – detection or process control means
Reexamination Certificate
2001-06-19
2002-09-24
Dang, Thi (Department: 1763)
Adhesive bonding and miscellaneous chemical manufacture
Differential fluid etching apparatus
With measuring, sensing, detection or process control means
C156S345100
Reexamination Certificate
active
06454899
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method for filling trenches.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconductive substrate. One technique for interconnecting devices on the same plane is to form a trench in an insulative layer (e.g., silicon dioxide or silicon nitride) and fill the trench with a conductive material (e.g., metal).
The semiconductor devices that comprise the integrated circuit must also be electrically isolated from one another. A common technique for forming isolation structures, referred to as shallow trench isolation, involves forming a trench in a substrate and filling the trench with an insulative material (e.g., silicon oxide).
Typically, trenches are filled by blanket depositing a layer over the trench topology and removing the portions of the layer outside of the trenches using a chemical mechanical polishing (CMP) technique. A chemical mechanical polishing process planarizes the layer to ease formation of subsequent process layers. Chemical mechanical polishing typically uses an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be disbursed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, the surface of the wafer is mechanically and chemically polished.
The deposited layer to be polished initially conforms to the underlying trench topology, leaving low areas (i.e., over the trench) and high areas (i.e., where no trench is present). The CMP process removes the high areas at a higher rate than the low areas, thus planarizing the surface. Due to the flexibility of the polishing pad and the presence of isotropic etchants in the polishing slurry, some etching of the low areas above the trenches occurs. If the thickness of the deposited layer is not sufficient, the low areas may be etched such that a portion of the material within the trench is undesirably removed, thus interfering with the function of the trench (i.e., either as a conductive member or as an isolation structure).
Often, there is no reliable endpoint available for stopping the anisotropic etch used to form the trench, and thus, the trench depth may vary from lot to lot or wafer to wafer. To account for this variation, a worst case trench depth is determined and the deposited layer thickness and polish parameters are selected to address this limiting case. As a result of this worst case approach, often more material is deposited and polished than is actually required for the particular trench depth of the wafer being processed. Such over deposition and over polishing decreases the throughput of the processing line by increasing the processing time required at these steps. Also, due to the flexibility of the polishing pad, it is possible that the high areas may be removed while a portion of the low areas remains extending beyond the trench. In such a case, the polishing pad will begin removing the substrate, albeit at a different rate than the deposited layer. This effect, commonly referred to as dishing the substrate, can have deleterious effects on the semiconductor device and result in it being discarded.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for filling a trench. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench.
Another aspect of the present invention is seen in a processing line including a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.
REFERENCES:
patent: 5590051 (1996-12-01), Yokozawa
patent: 5637351 (1997-06-01), O'Neal et al.
patent: 5724144 (1998-03-01), Muller et al.
patent: 6060370 (2000-05-01), Hsia et al.
patent: 6306669 (2001-10-01), Yano et al.
Campbell William J.
Christian Craig W.
Fulford H. Jim
Raeder Christopher H.
Sonderman Thomas
Advanced Micro Devices , Inc.
Dang Thi
Williams Morgan & Amerson P.C.
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